Nā hihia noi he nui o nā huahana ʻenehana, ʻepekema, a me nā lekiō olakino (ISM-RF) e hōʻike i ka papa kaapuni i paʻi ʻia hoʻonohonoho ʻia o kēia huahana maʻalahi i nā kīnā like ʻole.ʻIke pinepine ka poʻe i ka IC like i kau ʻia ma nā papa kaapuni ʻelua, ʻokoʻa loa nā ʻōuli hana. Variations in operating conditions, harmonic radiation, anti-interference ability, and start-up time can explain the importance of circuit board layout in a successful design.

This article lists the various design omissions, discusses the causes of each failure, and provides suggestions on how to avoid these design defects. I kēia pepa, fr-4 dielectric, 0.0625in mānoanoa papalua papa PCB ma ke ʻano he laʻana, ka hoʻokumu ʻana o ka papa kaapuni. Operating in different frequency bands between 315MHz and 915MHz, Tx and Rx power between -120dbm and +13dBm.

ʻAoʻao kuhikuhi

Ke kokoke aku kekahi mau mea hoʻokomo ʻelua (a i ʻole ʻelua mau laina PCB) kekahi i kekahi, e hanana pū kekahi. The magnetic field generated by the current in the first circuit excites the current in the second circuit (Figure 1). This process is similar to the interaction between the primary and secondary coils of a transformer. When two currents interact through a magnetic field, the voltage generated is determined by mutual inductance LM:

Ma hea, ʻo YB ke anakuhi uila i hoʻopili ʻia i loko o ka puni B, IA ʻo ia ka 1 i kēia manawa e hana ana ma ke kaapuni A. LM is very sensitive to circuit spacing, inductance loop area (i.e., magnetic flux), and loop direction. Therefore, the best balance between compact circuit layout and reduced coupling is the correct alignment of all inductors in the direction.

FIG. 1. It can be seen from magnetic field lines that mutual inductance is related to inductance alignment direction

The direction of circuit B is adjusted so that its current loop is parallel to the magnetic field line of circuit A. No kēia kumu, e like me ka perpendicular i hiki i kekahi i kekahi, e ʻoluʻolu e nānā i ka hoʻonohonoho kaapuni o ka papa haʻahaʻa FSK superheterodyne Receiver Evaluation (EV) papa (MAX7042EVKIT) (Kiʻi 2). The three inductors on the board (L3, L1 and L2) are very close to each other, and their orientation at 0°, 45° and 90° helps to reduce mutual inductance.

Kiʻi 2. Hōʻike ʻia ʻelua mau hoʻonohonoho PCB ʻokoʻa, kahi o nā mea i hoʻonohonoho ʻia i ke ala hewa (L1 a me L3), ʻoiai ʻoi aku ke kūpono o kekahi.

I ka hōʻuluʻulu ʻana, pono e mālama ʻia nā kumu aʻe:

ʻO ke ākea inductance e mamao loa i hiki.

Hoʻonohonoho ʻia nā Inductors ma nā kihi kūpono e hoʻoliʻiliʻi i ka crosstalk ma waena o nā inductors.

Alakaʻi i ka hoʻohui

E like me ke ʻano o ka hoʻokomo o ka hoʻokomo i ka hoʻopili ʻana i ka magnet, pēlā nō ka hoʻopili ʻana inā kokoke loa nā alakaʻi i kekahi i kekahi. Hoʻopuka pū kēia ʻano pilikia hoʻonohonoho i ka mea i kapa ʻia ka sensation mutual. ʻO kekahi o nā pilikia e hopohopo nui nei o ka huakaʻi RF ʻo ia ka uea o nā ʻāpana maʻalahi o ka ʻōnaehana, e like me ka pūnaewele hoʻopili hoʻokomo, ke kahawai resonant o ka mea loaʻa, ke kikowaena uila antenna o ka transmitter, etc.

ʻO ke ala o ka hoʻihoʻi e kokoke kokoke ana i ke ala nui o kēia manawa e hiki ai ke hoʻoliʻiliʻi i ka māno uila. This arrangement helps to reduce the current loop area. ʻO ke ala kūʻē haʻahaʻa haʻahaʻa kūpono no ka manawa hoʻihoʻi pinepine ka ʻāina ma lalo o ke kēpau – ka palena palena ʻana i ka wahi loop i kahi ʻāina kahi e hoʻonui ʻia ai ka mānoanoa o ka dielectric e ka lōʻihi o ke kēpau. Eia nō naʻe, inā ua hoʻokaʻawale ka ʻāina o ka honua, hoʻonui ka wahi o ka loop (Figure 3). For leads passing through the split region, the return current will be forced through the high resistance path, greatly increasing the current loop area. This arrangement also makes circuit leads more susceptible to mutual inductance.

Kaha 3. Hoʻopiha ka ʻāina nui i ka hoʻomaikaʻi ʻana i ka hana ʻōnaehana

No kahi mea hoʻokomo maoli, he hopena koʻikoʻi ka kuhikuhi alakaʻi i ka hoʻopili ʻana o ka māla ʻume mākenēki. Inā pono kokoke nā alakaʻi o ke kaapuni huehue i kēlā me kēia, ʻoi aku ka maikaʻi o ke kaulike ʻana i nā alakaʻi e hōʻemi i ka hoʻopili ʻana (Figure 4). If vertical alignment is not possible, consider using a guard line. No ka hoʻolālā uea pale, e ʻoluʻolu e nānā i ka pae a me ka hoʻopihapiha ʻana i ka ʻāpana lapaʻau ma lalo.

Figure 4. Similar to Figure 1, shows the possible coupling of magnetic field lines.

To sum up, the following principles should be followed when the plate is distributed:

Complete grounding should be ensured below the lead.

Sensitive leads should be arranged vertically.

If the leads must be arranged in parallel, ensure adequate spacing or use guard wires.

Grounding via

ʻO ka pilikia nui me ka hoʻonohonoho kaapuni RF ka maʻa mau ka impedance ʻano o ka pōʻaiapuni, me nā ʻāpana kaapuni a me kā lākou mau pilina. ʻO ke kēpau me ka uhi keleawe lahilahi e like ia me ka uea inductance a hana i kahi capacitance i hāʻawi ʻia me nā alakaʻi ʻē aʻe ma kahi kokoke. Hōʻike ka kēpau i ka inductance a me ka capacitance waiwai ke hele i loko o ka lua.

The through-hole capacitance mainly comes from the capacitance formed between the copper cladding on the side of the through-hole pad and the copper cladding on the ground, separated by a fairly small ring. Another influence comes from the cylinder of the metal perforation itself. Liʻiliʻi ka hopena o ka capacitance parasite a hana wale ia i kumu no ka loli o ka wikiwiki wikiwiki (ʻaʻole e kūkākūkā ʻia i kēia pepa).

ʻO ka hopena nui o ka puka ma o ka puka parasite i hoʻokumu ʻia e ke ʻano pilina pili like. Because most metal perforations in RF PCB designs are the same size as lumped components, the effect of electrical perforations can be estimated using a simple formula (FIG. 5) :

Where, LVIA is lumped inductance through hole; H is the height of the throughhole, in inches; ʻO D ke anawaena o ka throughhole, i nā ʻīniha 2.

Pehea e pale ai i nā kīnā ʻē aʻe i ka hoʻonohonoho PCB o nā papa pai

FIG. 5. PCB cross section used to estimate parasitic effects on through-hole structures

The parasitic inductance often has a great influence on the connection of bypass capacitors. Hāʻawi nā capacitors bypass bypass i nā kaapuni pōkole kiʻekiʻe pinepine ma waena o ka wahi e hoʻolako ai a me ke kūkulu ʻana, akā hiki i nā puka puka ʻole kūpono ke hoʻopili i ke ala haʻahaʻa ma waena o ka hoʻokumu a me ka wahi hoʻolako. A typical PCB through hole (d = 10 mil, h = 62.5 mil) is approximately equivalent to a 1.34nH inductor. Hāʻawi ʻia i ke alapine hana kūikawā o ka huahana ISM-RF, hiki i nā puka-lua ke hoʻopilikia i nā kaapuni koʻikoʻi e like me nā kaola resonant, nā kānana, a me nā pūnaewele like.

Kū aʻe nā pilikia ʻē aʻe inā kaʻana kaapuni kaapuni i nā lua, e like me nā lima ʻelua o kahi pūnaewele type – ʻano. ʻO kahi laʻana, ma ke kau ʻana i kahi lua kūpono e like me ka inductance lumped, ʻokoʻa ka skema like me ka hoʻolālā kaapuni kumu (FIG. 6). As with crosstalk of common current path 3, resulting in increased mutual inductance, increased crosstalk and feed-through.

How to avoid PCB design problems

Kiʻi 6. Kūpono vs. nā kuhikuhipuʻuone kūpono ʻole, aia nā “ala hōʻailona” kūpono i ka pōʻaiapuni.

To sum up, circuit layout should follow the following principles:

Ensure modeling of through-hole inductance in sensitive areas.

The filter or matching network uses independent through-holes.

Note that a thinner PCB copper-clad will reduce the effect of parasitic inductance through the hole.

Ka lōʻihi o ke kēpau

Paipai pinepine ka ʻikepili huahana Maxim ISM-RF i ka hoʻohana ʻana i kahi hoʻokomo pōkole loa pinepine hikiwawe e hoʻoliʻiliʻi i nā nalo a me nā radiation. Ma ka ʻaoʻao ʻē aʻe, hana pinepine ʻia ia mau nalowale e nā palena parasite non-ideal, no laila e hoʻopili ana ka inductance parasite a me ka capacitance i ka hoʻonohonoho kaapuni, a me ka hoʻohana ʻana i ke alakaʻi hiki pōkole loa e kōkua ai e hōʻemi i nā palena parasite. Typically, a 10 mil wide PCB lead with a distance of 0.0625in… From a FR4 board produces an inductance of approximately 19nH/in and a distributed capacitance of approximately 1pF/in. No kahi pūnaewele LAN / mixer me kahi 20nH inductor a me kahi capacitor 3pF, e loli loa ka waiwai o ka waiwai i ka wā e paʻa pono ai ke kaʻapuni a me ka hoʻonohonoho hoʻonohonoho.

Ipc-d-317a4 in ‘Institute for Printed Circuits’ provides an industry standard equation for estimating various impedance parameters of microstrip PCB. Ua hoʻololi ʻia kēia palapala i ka makahiki 2003 e IPC-2251 5, kahi e hāʻawi ai i kahi ʻano helu ʻoi aku ka pololei no nā alakaʻi PCB like ʻole. Online calculators are available from a variety of sources, most of which are based on equations provided by IPC-2251. The Electromagnetic Compatibility Lab at Missouri Institute of Technology provides a very practical method for calculating PCB lead impedance 6.

The accepted criteria for calculating the impedance of microstrip lines are:

I ke kumumanaʻo, εr ka dielectric mau o ke dielectric, h ke kiʻekiʻe o ke kēpau mai ke stratum, ʻo W ka laulā kēpau, a ʻo T ka mānoanoa kēpau (FIG. 7). Aia ka w / h ma waena o 0.1 a me 2.0 a εr ma waena o 1 a me 15, ua pololei loa nā hopena helu o kēia ʻano.

Figure 7. This figure is a PCB cross section (similar to Figure 5) and represents the structure used to calculate the impedance of a microstrip line.

In order to evaluate the effect of lead length, it is more practical to determine the detuning effect of ideal circuit by lead parasitical parameters. I kēia laʻana, kūkākūkā mākou i ka capacitance stray a me ka inductance. The standard equation of characteristic capacitance for microstrip lines is:

Pēlā nō, hiki ke helu ʻia ke ʻano inductance mai ka hoʻohālikelike ʻana ma o ka hoʻohana ʻana i ka hoʻohālikelike ma luna:

ʻO kahi laʻana, e noʻonoʻo i kahi mānoanoa PCB o 0.0625in. (h = 62.5 mil), 1 auneke kēpau pale pale keleawe (t = 1.35 mil), 0.01in. (w = 10 mil), a me kahi papa FR-4. E hoʻomaopopo he 4 farad / m (F / m) ka ε R o FR-4.35, akā hiki ke kau ʻia mai 4.0F / m a 4.7F / m. ʻO nā eigenvalues ​​i helu ʻia i kēia laʻana ʻo Z0 = 134 ω, C0 = 1.04pF / in, L0 = 18.7nH / in.

No AN ISM-RF hoʻolālā, kahi 12.7mm (0.5in) lōʻihi hoʻonohonoho o nā alakaʻi ma ka papa hiki ke hana i nā palena parasite ma kahi o 0.5pF a me 9.3nH (Kiʻi 8). ʻO ka hopena o nā palena parasite ma kēia pae ma ke kahawai resonant o ka mea loaʻa (ka loli o ka huahana LC) i hopena i 315MHz ± 2% a i ʻole 433.92mhz ± 3.5% hoʻololi. Ma muli o ka capacitance hou a me ka inductance i hoʻokumu ʻia e ka hopena parasitic o ke kēpau, piʻi ka piko o ke alapine oscillation 315MHz i ka 312.17mhz, a piʻi ka piko o ka 433.92mhz oscillation frequency i 426.6mhz.

Another example is the resonant channel of Maxim’s superheterodyne receiver (MAX7042). The recommended components are 1.2pF and 30nH at 315MHz; At 433.92MHz, it is 0pF and 16nH. E helu i ke alapine oscillation o ke kaapuni resonant ma o ka hoʻohana ʻana i ka hoʻohālikelike.

Pono e hoʻopili i ka loiloi o ka pōʻaiapuni resonant o ka pā i nā hopena parasitic o ka pūʻolo a me ka hoʻonohonoho, a me nā palena parasite 7.3PF a me 7.5PF i ka helu ʻana i ke alapine resonant 315MHz. E hoʻomaopopo he hōʻike ka huahana LC i ka capacitance lumped.

I ka hōʻuluʻulu ʻana, pono e mālama ʻia nā kumu aʻe:

E mālama i ke alakaʻi i ka pōkole e like me ka hiki.

E hoʻokau i nā kaapuni kī i kokoke i ka hāmeʻa e hiki ai.

Uku uku ʻia nā mea nui e like me ka parasitism ʻōnaehana maoli.

Ka honua a me ka hoʻopiha ʻana i ka lāʻau

The grounding or power layer defines a common reference voltage that supplies power to all parts of the system through a low resistance path. ʻO ke kaulike ʻana i nā māla uila āpau i kēia ala e hana i kahi ʻano pale maikaʻi.

Kū pololei ke kahe pololei i ke kahe ma ke ala kūʻē haʻahaʻa. Ma ke ala like, ke kahe mau ʻo ke alapine kiʻekiʻe ma waena o ke ala me ka pale haʻahaʻa. So, for a standard PCB microstrip line above the formation, the return current tries to flow into the ground region directly below the lead. As described in the lead coupling section above, the cut ground area introduces various noises that increase crosstalk either through magnetic field coupling or by converging currents (Figure 9).

Pehea e pale ai i nā kīnā ʻē aʻe i ka hoʻonohonoho PCB o nā papa pai

FIG. 9. Keep the formation intact as much as possible, otherwise the return current will cause crosstalk.

Filled ground, also known as guard lines, is commonly used in circuits where continuous grounding is difficult to lay or where shielding sensitive circuits is required (FIG. 10). The shielding effect can be increased by placing grounding holes (i.e. hole arrays) at both ends of the lead or along the lead. 8. Mai kāwili i ka uea kiaʻi me ke kēpau i hoʻolālā ʻia e hāʻawi i kahi ala hoʻi i kēia manawa. Hiki i kēia hoʻonohonoho ke hoʻolauna i ka crosstalk.

Pehea e pale ai i nā kīnā ʻē aʻe i ka hoʻonohonoho PCB o nā papa pai

ANA. 10. Pono ka hoʻolālā ʻōnaehana RF e hōʻalo i nā uea keleawe lana lana, keu hoʻi inā koi ʻia ka sheathing keleawe.

ʻAʻole i hoʻokumu ʻia ka ʻāpana keleawe keleawe (lana) a i ʻole hoʻokumu wale ʻia ma ka wēlau hoʻokahi, kahi e kaupalena ai i kona pono. In some cases, it can cause unwanted effects by forming parasitic capacitance that changes the impedance of the surrounding wiring or creates a “latent” path between circuits. I ka pōkole, inā e kau ʻia kahi ʻāpana o ke keleawe keleawe (nā kelepaʻi hōʻailona ʻole kaapuni) ma ka papa kaapuni e hōʻoia i ka mānoanoa o ka plating paʻa. Pono e hōʻalo i nā wahi keleawe ʻia e pili ana i ka hoʻolālā kaapuni.

ʻO ka hope, e noʻonoʻo pono i nā hopena o kēlā me kēia wahi o ka honua kokoke i ka antenna. E loaʻa i kekahi antenna monopole ka ʻāina, ka hoʻopili a me nā lua ma ke ʻano he kaulike o ka ʻōnaehana, a me nā uea kaulike ʻole kūpono e hoʻopili i ka pono radiation a me ke kuhikuhi o ka antenna (radiation template). Therefore, the ground area should not be placed directly below the monopole PCB lead antenna.

I ka hōʻuluʻulu ʻana, pono e mālama ʻia nā kumu aʻe:

Hāʻawi i nā ʻāpana pae hoʻomau kū mau a me ka haʻahaʻa i ka hiki.

Hoʻokumu ʻia nā wēlau ʻelua o ka laina hoʻopihapiha, a hoʻohana ʻia kahi lālani puka ākea i kahi hiki.

Mai lana i ka uea kāʻei keleawe kokoke i ka pōʻai RF, mai waiho i ke keleawe a puni ka pōʻai RF.

Inā loaʻa i nā papa kaapuni he mau papa he nui, ʻoi aku ka maikaʻi e hoʻomoe i kahi lepo ma waena o ka puka ke hala ke kaula hōʻailona mai kekahi ʻaoʻao a i kekahi ʻaoʻao.

Ka nui o ke aniani capacitance

Parasitic capacitance will cause the crystal frequency to deviate from the target value 9. No laila, e ukali ʻia kekahi mau alakaʻi ākea e hoʻoliʻiliʻi i ka capacitance ʻauana o nā kui aniani, nā pale, nā kaula, a i ʻole nā ​​pilina i nā hāmeʻa RF.

The following principles should be followed:

ʻO ka pilina ma waena o ka aniani a me ka pono RF e like me ka pōkole e like me ka hiki.

Keep the wiring from each other as far as possible.

Inā nui ka capacitance shunt parasite, hemo i ka ʻāina pae ma lalo o ke aniani.

Hoʻohui uea Planar

Planar wiring or PCB spiral inductors are not recommended. Typical PCB manufacturing processes have certain inaccuracies, such as width and space tolerances, which greatly affect the accuracy of component values. No laila, ʻo ka hapa nui o nā mea hoʻokomo a kiʻekiʻe Q nā ʻano ʻeha. ʻO ka lua, hiki iā ʻoe ke koho i ka multilayer ceramic inductor, hoʻolako ʻia nā huahana capacitor multilayer chip capacitor i kēia huahana. Eia naʻe, koho kekahi mau mea hoʻolālā i nā inductors spiral ke pono lākou. The standard formula for calculating planar spiral inductance is usually Wheeler’s formula 10:

ʻAuhea, ʻo ke anapuni radius o ka wili, i nā ʻīniha; ʻO N ka helu o nā huli; ʻO C ka laulā o ke kumu coil (router-rinner), i nā ʻīniha. Ke coil c “0.2a 11, ka pololei o ke ana helu ma waena o 5%.

Hiki ke hoʻohana ʻia nā inductors spiral Single-layer of square, hexagonal, a i ʻole nā ​​ʻano ʻē aʻe. Hiki ke loaʻa nā hoʻokokoke maikaʻi loa e hoʻohālikelike i ka indarment planar ma nā wafers huila hoʻohui. I mea e hoʻokō ai i kēia pahuhopu, hoʻololi ʻia ke kumumanaʻo Wheeler maʻamau e loaʻa ai kahi ʻano koho loiloi inductance kūpono no ka liʻiliʻi liʻiliʻi a me ka nui o ka nui 12.

ʻAuhea, ρ ka lakio hoʻopiha :; ʻO N ka helu o nā huli, a ʻo dAVG ke anawaena waena:. No nā pāpale huinahā, K1 = 2.36, K2 = 2.75.

Nui nā kumu e hōʻalo ai i ka hoʻohana ʻana i kēia ʻano inductor, a ʻo ka hopena ma muli o ka hoʻemi ʻia o nā waiwai inductance ma muli o nā palena o ka lewa. The main reasons for avoiding planar inductors are limited geometry and poor control of critical dimensions, which makes it impossible to predict inductor values. Eia hou, paʻakikī e mālama i nā kumukūʻai inductance maoli i ka wā o ka hana ʻana o PCB, a mālama pū kekahi i ka leo i kekahi mau ʻāpana o ke kaapuni.