Tele tusi talosaga mataupu o alamanuia, faasaienisi, ma fomai leitio taimi masani (ISM-RF) oloa faʻaalia o le lolomi laupapa matagaluega O le faʻatulagaina o nei oloa e faigofie ona faʻaleagaina.E masani ona iloa e tagata o le tutusa IC faʻapipiʻi luga o lua eseese matagaluega laupapa, faʻailoga faʻailoga o le a matua eseʻese lava. Variations in operating conditions, harmonic radiation, anti-interference ability, and start-up time can explain the importance of circuit board layout in a successful design.

This article lists the various design omissions, discusses the causes of each failure, and provides suggestions on how to avoid these design defects. I lenei pepa, fr-4 dielectric, 0.0625in mafiafia faʻalua vaega PCB o se faʻataʻitaʻiga, o le matagaluega laupapa faʻavaeina. Operating in different frequency bands between 315MHz and 915MHz, Tx and Rx power between -120dbm and +13dBm.

Faʻatonuga le gaoia

A lua inductors (po o le lua laina PCB) e latalata i le tasi, o le a tupu faʻatasi inductance. The magnetic field generated by the current in the first circuit excites the current in the second circuit (Figure 1). This process is similar to the interaction between the primary and secondary coils of a transformer. When two currents interact through a magnetic field, the voltage generated is determined by mutual inductance LM:

Ole mea lea, ole YB ole voltage sese na tui ile matagaluega B, IA o le taimi nei 1 o loʻo galue ile matagaluega A. LM is very sensitive to circuit spacing, inductance loop area (i.e., magnetic flux), and loop direction. Therefore, the best balance between compact circuit layout and reduced coupling is the correct alignment of all inductors in the direction.

FIG. 1. It can be seen from magnetic field lines that mutual inductance is related to inductance alignment direction

The direction of circuit B is adjusted so that its current loop is parallel to the magnetic field line of circuit A. Mo lenei mafuaʻaga, tusa lava pe mafai i le tasi ma le isi, faʻamolemole vaʻai i le matagaluega faʻatulagaina o le maualalo paoa FSK superheterodyne Receiver Evaluation (EV) laupapa (MAX7042EVKIT) (Ata 2). The three inductors on the board (L3, L1 and L2) are very close to each other, and their orientation at 0°, 45° and 90° helps to reduce mutual inductance.

Ata 2. Lua faʻataʻatiaga PCB eseese o loʻo faʻaalia, o le tasi o ia elemeni o loʻo faʻatulagaina i le itu sese (L1 ma le L3), aʻo leisi e sili ona talafeagai.

To sum up, the following principles should be followed:

O le inductance spacing tatau ona mamao i le mea e mafai ai.

Inductors e faʻatulagaina i itu taumatau e faʻaititia ai crosstalk i le va o inductors.

Taʻitaʻi le fesoʻotaʻiga

E pei lava o le faʻamasaniina o mea faʻapipiʻi e aʻafia ai le faʻapipiʻiina o maneta, e faʻapena foi le fesoʻotaʻiga pe afai e latalata tele le taʻitaʻi i le tasi. O lenei ituaiga faʻafitauli faʻafitauli e maua ai foʻi le mea e taʻua o le lagona faʻatasi. O se tasi o faʻafitauli e sili ona atugalu i ai le matagaluega o le RF o le faʻapipiʻiina o vaega maaleale o le polokalama, e pei o le fesoʻotaʻiga i totonu o fesoʻotaʻiga, ala leo resonant o le tagata e taliaina, antenna tutusa fesoʻotaʻiga o le transmitter, ma isi.

O le toe foʻi auala nei e tatau ona latalata i le autu auala nei pe a mafai e faʻaititia ai le radiation maneta fanua. This arrangement helps to reduce the current loop area. O le auala maualalo maualalo teteʻe mo le toe foʻi nei o masani lava o le eleele itulagi lalo o le taʻitaʻiga – lelei faʻatapulaʻaina le loop eria i se itulagi o le mafiafia o le dielectric e faʻateleina e le umi o le taʻimua. Ae peitaʻi, a vaeluaina le laufanua o le eleele, ona faʻateleina lea o le itu e faʻatautaia (Ata 3). For leads passing through the split region, the return current will be forced through the high resistance path, greatly increasing the current loop area. This arrangement also makes circuit leads more susceptible to mutual inductance.

Ata 3. Atoa le vaega tele o le eleele e fesoasoani e faʻaleleia atili ai le faʻaogaina o le tino

Mo se inductor moni, taʻimua faʻatonuga foi ei ai se taua aafiaga i maneta fanua soʻotaga. Afai e tatau ona latalata le tasi i le isi itu o le taʻamilosaga maʻaleʻale, e sili atu le faʻaugatasia o taʻitaʻiga agai i luga e faʻaititia ai le fesoʻotaʻiga (Ata 4). If vertical alignment is not possible, consider using a guard line. For protection wire design, please refer to the grounding and filling treatment section below.

Figure 4. Similar to Figure 1, shows the possible coupling of magnetic field lines.

To sum up, the following principles should be followed when the plate is distributed:

Complete grounding should be ensured below the lead.

Sensitive leads should be arranged vertically.

If the leads must be arranged in parallel, ensure adequate spacing or use guard wires.

Grounding via

O le faʻafitauli autu i le RF matagaluega faʻataʻitaʻiga e masani lava o le suboptimal uiga faʻafitauli o le matagaluega, e aofia ai le matagaluega vaega ma a latou fesoʻotaʻiga. O le taʻimua ma le manifinifi apamemea ufiufi e tutusa ma le inductance uaea ma fausia ai se tufatufaina capacitance ma isi taʻitaʻi i le latalata ane. O le taʻimua foi faʻaalia inductance ma capacitance meatotino a o pasia le pu.

The through-hole capacitance mainly comes from the capacitance formed between the copper cladding on the side of the through-hole pad and the copper cladding on the ground, separated by a fairly small ring. Another influence comes from the cylinder of the metal perforation itself. O le aʻafiaga o le parasite capacitance e masani ona laʻititi ma e masani naʻo le faʻatupuina o fesuiaʻiga o laina televise (e le talanoaina i lenei pepa).

O le sili ona tele aafiaga o le ala-lua o le parasite inductance mafua mai i le tutusa fesoʻotaʻiga auala. Because most metal perforations in RF PCB designs are the same size as lumped components, the effect of electrical perforations can be estimated using a simple formula (FIG. 5) :

Where, LVIA is lumped inductance through hole; H is the height of the throughhole, in inches; O le lautele o le alualu i luga, i inisi 2.

Faʻafefea ona aloese mai faʻaletonu eseese i PCB faʻatulagaina o lolomi laupapa

FIG. 5. PCB cross section used to estimate parasitic effects on through-hole structures

The parasitic inductance often has a great influence on the connection of bypass capacitors. Ole auala sologa lelei e maua ai matagaluega puʻupuʻu i le va ole sapalai ma le faʻavae, ae ole auala lelei e ala ile-pu e ono aʻafia ai ile ala maualalo ile va ile faʻavae male vaega sapalai. A typical PCB through hole (d = 10 mil, h = 62.5 mil) is approximately equivalent to a 1.34nH inductor. Tuuina atu i le faʻapitoa taimi o faʻagaioiga o le oloa ISM-RF, o le ala-pu mafai ona afaina ai matagaluega maaleale e pei o resonant auala liʻo, faʻamamaina, ma tutusa fesoʻotaʻiga.

O isi faʻafitauli e aliae mai pe a fefaʻasoaaʻi vaeluaga pu, pei o lima e lua o le π – ituaiga upega. Mo se faʻataʻitaʻiga, o le tuʻuina o se pu e fetaui lelei ma le faʻaopoopoina o vaega, o le faʻataʻitaʻiga tutusa e ese mai le uluaʻi taʻamilosaga (FIG.6). As with crosstalk of common current path 3, resulting in increased mutual inductance, increased crosstalk and feed-through.

How to avoid PCB design problems

Ata 6. Lelei ma le le lelei fale tusiata, o loʻo i ai ni “auala faʻailo” i le matagaluega.

To sum up, circuit layout should follow the following principles:

Ensure modeling of through-hole inductance in sensitive areas.

The filter or matching network uses independent through-holes.

Note that a thinner PCB copper-clad will reduce the effect of parasitic inductance through the hole.

O le umi o le taʻimua

O faʻamatalaga o oloa a Maxim ISM-RF e masani ona fautuaina ai le faʻaaogaina o se sao puʻupuʻu ma alualu i luma e faʻaititia ai leiloa ma leisa. I leisi itu, o ia tupe leiloa e masani lava ona mafua mai i le le lelei lelei parasite, o lona uiga laʻititi parasite inductance ma capacitance aʻafia le matagaluega faʻataʻamilosaga, ma le faʻaaogaina o le puʻupuʻu mafai mafai fesoasoani fesoasoani e faʻaititia ai le parasitic tapulaʻa. Typically, a 10 mil wide PCB lead with a distance of 0.0625in… From a FR4 board produces an inductance of approximately 19nH/in and a distributed capacitance of approximately 1pF/in. Mo se LAN / palu faʻamalama ma se 20nH inductor ma se 3pF capacitor, o le aoga vaega taua o le a matua afaina pe a fai o le matagaluega ma vaega faʻatulagaina e matua puʻupuʻu.

Ipc-d-317a4 in ‘Institute for Printed Circuits’ provides an industry standard equation for estimating various impedance parameters of microstrip PCB. O lenei pepa na suia i le 2003 e le IPC-2251 5, lea e maua ai se auala saʻo e sili atu ona saʻo mo taʻitaʻi eseese PCB. Online calculators are available from a variety of sources, most of which are based on equations provided by IPC-2251. The Electromagnetic Compatibility Lab at Missouri Institute of Technology provides a very practical method for calculating PCB lead impedance 6.

The accepted criteria for calculating the impedance of microstrip lines are:

I le metotia, εr o le dielectric tumau o le dielectric, h o le maualuga o le taʻimua mai le stratum, W o le lautele lautele, ma T o le taʻimua mafiafia (ATA. 7). A o le w / h i le va o le 0.1 ma le 2.0 ma le is o loʻo i le va o le 1 ma le 15, o le faʻatatauina o iʻuga o lenei auala e matua saʻo lava.

Figure 7. This figure is a PCB cross section (similar to Figure 5) and represents the structure used to calculate the impedance of a microstrip line.

In order to evaluate the effect of lead length, it is more practical to determine the detuning effect of ideal circuit by lead parasitical parameters. I lenei faʻataʻitaʻiga, tatou te talanoaina ai le seʻe viviʻi ma le faʻaofiina. The standard equation of characteristic capacitance for microstrip lines is:

E faʻapena foi, o le uiga faʻavae mafai ona fuafuaina mai le faʻatusatusaga i le faʻaaogaina o le faʻatusa luga:

Mo se faʻataʻitaʻiga, manatu le mafiafia PCB o le 0.0625in. (h = 62.5 mil), 1 aunese ‘apamemea ufiufi’ apamemea (t = 1.35 mil), 0.01in. (w = 10 mil), ma le laupapa FR-4. Manatua o le ε R o FR-4 e masani ona 4.35 farad / m (F / m), ae mafai ona amata mai le 4.0F / m i le 4.7F / m. O le eigenvalues ​​fuafuaina i lenei faʻataʻitaʻiga o Z0 = 134 ω, C0 = 1.04pF / in, L0 = 18.7nH / in.

Mo se mamanu ISM-RF, o le 12.7mm (0.5in) umi faʻatulagaina o taʻi luga o le laupapa e mafai ona maua ai faʻasologa faʻasologa o le tusa 0.5pF ma le 9.3nH (Ata 8). O le iʻuga o faʻataʻitaʻiga parasite i lenei tulaga i luga o le laina resonant o le tagata e taliaina (fesuiaʻiga o oloa LC) e ono iʻu ai i le 315MHz ± 2% poʻo le 433.92mhz ± 3.5% fesuiaʻiga. Ona o le faʻaopoopo capacitance ma inductance mafua mai i le parasitic aafiaga o le taʻimua, o le tumutumu o le 315MHz oscillation taimi e oʻo atu 312.17mhz, ma le tumutumu o le 433.92mhz oscillation taimi masani taunuu 426.6mhz.

Another example is the resonant channel of Maxim’s superheterodyne receiver (MAX7042). The recommended components are 1.2pF and 30nH at 315MHz; At 433.92MHz, it is 0pF and 16nH. Fuafua le oscillation taimi o resonant matagaluega e ala i le faʻaaogaina o le faʻatusa:

O le iloiloga o le liʻo liʻo o le ipu e tatau ona aofia ai le faʻamaʻi aafiaga o le afifi ma le faʻatulagaina, ma le faʻamamafaʻafaiga parasite o le 7.3PF ma le 7.5PF faʻatulagaina pe a fuafuaina le 315MHz resonant taimi. Manatua o le oloa LC o loʻo faʻatusalia i le mafai gafatia.

I le aotelega, o mataupu faavae nei e tatau ona mulimulitaʻia.

Taofi le taʻimua i le vave e mafai ai.

Tuʻu faʻasologa ki i se mea latalata i le masini pe a mafai.

O vaega taua o loʻo totogiina e tusa ma le faʻatulagaina o le parasitism.

Eleele ma faʻatumu togafitiga

The grounding or power layer defines a common reference voltage that supplies power to all parts of the system through a low resistance path. Faʻatulagaina uma eletise fanua i lenei auala maua ai se lelei talipupuni auala.

O taimi faʻatonu i taimi uma e masani ona masani ona tafe i se auala maualalo le teteʻe. I le auala lava e tasi, maualuga-taimi nei alualu i luma preferentially tafe i le ala ma le maualalo teteʻe. So, for a standard PCB microstrip line above the formation, the return current tries to flow into the ground region directly below the lead. As described in the lead coupling section above, the cut ground area introduces various noises that increase crosstalk either through magnetic field coupling or by converging currents (Figure 9).

Faʻafefea ona aloese mai faʻaletonu eseese i PCB faʻatulagaina o lolomi laupapa

FIG. 9. Keep the formation intact as much as possible, otherwise the return current will cause crosstalk.

Filled ground, also known as guard lines, is commonly used in circuits where continuous grounding is difficult to lay or where shielding sensitive circuits is required (FIG. 10). The shielding effect can be increased by placing grounding holes (i.e. hole arrays) at both ends of the lead or along the lead. 8. Aua le faʻafefiloi le uaea leoleo ma le taʻitaʻi fuafuaina e maua ai se toe auala auala. Lenei faʻatulagaga mafai faʻalauiloa crosstalk.

Faʻafefea ona aloese mai faʻaletonu eseese i PCB faʻatulagaina o lolomi laupapa

ATA 10. O le RF faiga mamanu tatau ona aloese mai opeopea ‘apamemea ofu uaea, aemaise pe a fai e manaʻomia sheathing’ apamemea.

O le vaega ‘apamemea-faʻaofuina e le faʻavaeina (opeopea) pe faʻavaeina naʻo le tasi pito, lea e faʻatapulaʻaina lona aoga. In some cases, it can cause unwanted effects by forming parasitic capacitance that changes the impedance of the surrounding wiring or creates a “latent” path between circuits. I se faapuupuuga, pe a fai o se fasi ‘apamemea cladding (le taʻamilo faailoilo faʻailoga) o loʻo faʻataʻatia luga o le matagaluega laupapa e mautinoa ai le ogatasi plating mafiafia. E tatau ona aloese mai vaega e fai i le ‘apamemea aʻo latou aʻafia le mamanu o le matagaluega.

I le iuga, ia mautinoa ia mafaufau i le aʻafiaga o soʻo se eleele eleele latalata i le velo. Soʻo se monopole velo o le ai ai le eleele itulagi, faʻapipiʻiina ma pu o se vaega o le paleni paleni, ma le le lelei paleni faʻafesoʻotaʻiga o le a aʻafia ai le radiation lelei ma faʻatonuga o le antenna (radiation template). Therefore, the ground area should not be placed directly below the monopole PCB lead antenna.

To sum up, the following principles should be followed:

Tuʻuina atu faʻaauau ma maualalo-teteʻe eleele faʻavae eleele i le mamao e mafai ai.

O laina uma e lua o le faʻatumuina o laina ua faʻavaeina i lalo, ma o se faʻaaoga i totonu o le pu e faʻaaoga i le mamao e mafai ai.

Aua le opeopea apamemea faʻaofuofu uaea latalata RF matagaluega, aua le faataʻoto apamemea faataamilo RF.

Afai o le matagaluega laupapa o loʻo i ai le tele o faaputuga, e sili ona lelei le tuʻu o se eleele i totonu o le pu pe a o le faʻailoga uaea pasi mai le tasi itu i le isi.

Ovaa tioata capacitance

Parasitic capacitance will cause the crystal frequency to deviate from the target value 9. O le mea lea, e tatau ona mulimulitaʻia ni faʻatonuga lautele e faʻaititia ai le se ese capacitance o tioata pin, pads, uaea, poʻo fesoʻotaʻiga i masini RF.

The following principles should be followed:

O le fesoʻotaʻiga i le va o le tioata ma le RF masini e tatau ona sili atu ona puʻupuʻu mafai.

Keep the wiring from each other as far as possible.

Afai o le shunt parasite capacitance e tele tele, aveʻese le faʻavae vaega lalo o le tioata.

Planar wiring inductance

Planar wiring or PCB spiral inductors are not recommended. Typical PCB manufacturing processes have certain inaccuracies, such as width and space tolerances, which greatly affect the accuracy of component values. Therefore, most controlled and high Q inductors are wound type. Lona lua, e mafai ona e filifilia multilayer ceramic inductor, multilayer chip capacitor gaosi oloa latou saunia foi lenei oloa. E ui i lea, o nisi tagata mamanu latou te filifilia ni tamaʻi totoga pe a tatau. The standard formula for calculating planar spiral inductance is usually Wheeler’s formula 10:

O fea, o le averesi faataamilosaga o le coil, i inisi; N o le numera o avanoa; C o le lautele o le autu coil (router-rinner), i inisi. A o le coil c “0.2a 11, o le saʻo o le auala metotia i totonu o le 5%.

E mafai ona faʻaaogaina faʻatulagaina faʻasolosolo tasi-vaega o sikuea, hexagonal, poʻo isi foliga. Lelei tele faʻatusatusaga mafai ona maua e faʻataʻitaʻi planar inductance i luga o tuʻufaʻatasia solo areto. Ina ia mafai ona ausia lenei sini, o le masani fuaʻiga fua faatatau ua suia e maua ai se vaalele inductance fuafuaina metotia talafeagai mo laiti laʻititi ma sikuea tele 12.

O fea, ρ o le faʻatumuina faʻatatau:; N o le numera o liliu, ma dAVG o le averesi averesi:. Mo sikuea sikuea, K1 = 2.36, K2 = 2.75.

E tele mafuaʻaga e aloese ai mai le faʻaaogaina o lenei ituaiga o inductor, lea e masani ona mafua ai le faʻaititia inductance aoga ona o avanoa avanoa. The main reasons for avoiding planar inductors are limited geometry and poor control of critical dimensions, which makes it impossible to predict inductor values. I se faʻaopopoga, inductance moni taua e faigata ona faʻatonutonuina i le taimi o PCB gaosiga, ma inductance faʻasolosolo foi e ulugaliʻi pisapisao i isi vaega o le matagaluega.