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Considerations for high-speed system PCB design related to serdes applications are as follows:

(1) Microstrip and Stripline wiring.

Microstrip lines are wiring over the outer signal layer of a reference plane (GND or Vcc) separated by electrical media to minimize delays; The ribbon wires are routed in the inner signal layer between the two reference planes (GND or Vcc) for greater capacitive reactance, easier impedance control and cleaner signal, as shown in the figure.

Microstrip line and strip line are best for wiring

(2) high-speed differential signal wiring.

Common wiring methods for high-speed differential signal pair include Edge Coupled microstrip (top layer), Edge Coupled ribbon line (embedded signal layer, suitable for high-speed SERDES differential signal pair) and Broadside Coupled microstrip, as shown in the figure.

High speed differential signal pair wiring

(3) bypass capacitance (BypassCapacitor).

Bypass capacitor is a small capacitor with very low series impedance, which is mainly used to filter high frequency interference in high speed conversion signals. There are three kinds of bypass capacitors mainly applied in FPGA system: high-speed system (100MHz~1GHz) commonly used bypass capacitors range from 0.01nF to 10nF, generally distributed within 1cm from Vcc; Medium-speed system (more than ten MHZ 100MHz), the common bypass capacitor range is 47nF to 100nF tantalum capacitor, generally within 3cm of Vcc; Low-speed system (less than 10 MHZ), the commonly used bypass capacitor range is 470nF to 3300nF capacitor, the layout on the PCB is relatively free.

(4) Capacitance optimal wiring.

Capacitor wiring can follow the following design guidelines, as shown.

Capacitive optimal wiring

Capacitive pin pads are connected using large size through holes (Via) to reduce coupling reactance.

Use a short, wide wire to connect the pad of the capacitor pin to the hole, or directly connect the pad of the capacitor pin to the hole.

LESR capacitors (Low Effective Series Resistance) were used.

Each GND pin or hole should be connected to the ground plane.

(5) Key points of high-speed system clock wiring.

Avoid zigzag winding and route clocks as straight as possible.

Try to route in a single signal layer.

Do not use through-holes as much as possible, as through-holes will introduce strong reflection and impedance mismatches.

Use microstrip wiring in the top layer as much as possible to avoid the use of holes and minimize signal delay.

Place the ground plane near the clock signal layer as far as possible to reduce noise and crosstalk. If an internal signal layer is used, the clock signal layer can be sandwiched between two ground planes to reduce noise and interference. Shorten signal delay.

The clock signal should be correctly impedance matched.

(6) Matters needing attention in high-speed system coupling and wiring.

Note the impedance matching of the differential signal.

Note the width of the differential signal line so that it can tolerate 20% of the signal rise or fall time.

With appropriate connectors, the rated frequency of the connector should meet the highest frequency of the design.

Edge-couple coupling should be used as far as possible to avoid broadside-couple coupling, 3S fractional rule should be used to avoid over-coupling or crossword.

(7) Notes on noise filtering for high-speed systems.

Reduce low frequency interference (below 1KHz) caused by power source noise, and add shielding or filtering circuit at each power source access end.

Add 100F electrolytic capacitor filter at each place where the power supply enters the PCB.

To reduce high-frequency noise, place as many decoupling capacitors at each Vcc and GND as possible.

Lay out the Vcc and GND planes in parallel, separate them with dielectrics (such as FR-4PCB), and lay out bypass capacitors in other layers.

(8) High speed system Ground Bounce

Try to add a decoupling capacitor to each Vcc/GND signal pair.

An external Buffer is added to the output end of high-speed reversal signals such as counters to reduce the requirement of driving capacity.

The Slow Slew (low-rise-slope) mode was set for output signals that did not require harsh speed.

Control load reactance.

Reduce the clock flipping signal, or distribute it as evenly as possible around the chip.

The signal that flips frequently is as close to the GND pin of the chip as possible.

The design of synchronous timing circuit should avoid the instantaneous reversal of output.

Diverting the power supply and the ground can play a role in the overall inductance.