Afai i lenei atamai tausaga, i lenei matata, oe manaʻo ia i ai se tomai i le FPGA, o lona uiga o le lalolagi o le a tuʻulafoaʻia oe, O le Times o le a tuʻulafoaʻia oe.

Mafaufauga mo le televave faiga PCB design related to serdes applications are as follows:

(1) Mikerosekope ma Stripline uaea.

O laina mikerosipolo o loʻo uaea i luga atu o le vaega o faʻailo o loʻo iai se vaalele faʻasino (GND poʻo Vcc) vavaeʻese e ala o faʻasalalauga eletise e faʻaititia ai le tolopo; O uaea lipine o loʻo faʻataʻamiloina i totonu o le vaega faʻailoilo i totonu o le va o vaʻalele e lua (GND poʻo Vcc) mo le tele o le gaioiga o le capacitive, e faigofie ai ona faʻatonutonu ma faʻamama le faʻailo, e pei ona faʻaalia i le ata.

Ole laina micropipipi ma fasi laina e sili ona lelei mo uaea

(2) televave saosaoa faʻailoga laina.

Masani metotia metotia mo maualuga-saosaoa eseesega faʻailoilo paʻaga aofia Edge faʻapipiʻi microstrip (pito i luga vaega), Edge Faʻalua laina lipine (faapipiiina faʻailoga vaega, talafeagai mo maualuga-saosaoa SERDES eseesega faʻailoga paʻu) ma Broadside Faʻatasi microstrip, e pei ona faʻaalia i le ata.

Maualuga saosaoa eseesega faʻailoga paina paipa

(3) aloese capacitance (BypassCapacitor).

Bypass capacitor o se laʻititi capacitor ma le laʻititi maualalo faʻafitauli impedance, lea e masani ona faʻaaogaina e faʻamama ai le maualuga o taimi e faʻalavelave ai i le saoasaoa o le liua o faʻailo. E tolu ituaiga o bypass capacitors masani lava ona faʻaaogaina i le FPGA system: maualuga-saosaoa system (100MHz ~ 1GHz) masani faʻaaoga bypass capacitors amata mai 0.01nF i le 10nF, masani tufatufaina i totonu o le 1cm mai Vcc; Feololo-saosaoa faiga (sili atu ma le sefulu MHZ 100MHz), o le masani bypass capacitor laina o 47nF i le 100nF tantalum capacitor, masani i totonu o le 3cm o Vcc; Laʻititi-saoasaoa faiga (lalo ifo o le 10 MHZ), o le masani faʻaaogaina o le capacitor range o le 470nF i le 3300nF capacitor, o le faʻatulagaga i luga o le PCB e fai fua.

(4) Capacitance sili ona lelei uaea.

Capacitor wiring can follow the following design guidelines, as shown.

Capacitive sili ona lelei uaea

Capacitive pin pads e fesoʻotaʻi faʻaaogaina tele i le pu (Via) e faʻaititia ai le fesoʻotaʻi reactance.

Use a short, wide wire to connect the pad of the capacitor pin to the hole, or directly connect the pad of the capacitor pin to the hole.

LESR capacitors (Low Effective Series Resistance) were used.

Taitasi GND pine po o le pu e tatau ona fesoʻotaʻi i le eleele vaʻalele.

(5) Manatu autu o maualuga-saosaoa faʻasologa uati faʻamalama.

Aloʻese mai zigzag faamaapeina ma auala uati saʻo i le mea e mafai ai.

Taumafai e auala i se tasi faʻailoga faailo.

Aua le faʻaaogaina-tele-pu i le mea sili e mafai ai, aua o totonu-pupu o le a faʻalauiloaina malosi malosiaga ma faʻafetaui sese.

Faʻaaoga le microstrip wiring i le pito i luga o le vaega i le mea e gata ai le mafai e aloese ai mai le faʻaaogaina o pu ma faʻaititia le tuai faʻataga.

Tuʻu le eleele vaʻalele latalata i le uati faailo vaega i le mamao e mafai ai e faʻaititia le pisapisao ma crosstalk. Afai e faʻaaogaina se vaega o faʻailo i totonu, e mafai ona sosolo le faʻailo o le uati i le va o vaalele e lua e faʻaitiitia ai le pisapisao ma le faʻalavelave. Faʻapuʻupuʻu faʻailo faʻatuai.

O le uati faailo e tatau ona sao faʻafetaui.

(6) Mataupu manaʻomia le faʻalogo i maualuga-saosaoa soʻoga faʻafesoʻotaʻi ma wiring.

Note the impedance matching of the differential signal.

Matau le lautele o le eseʻesega laina faʻailo ina ia mafai tolerate 20% o le faʻailoga tulaʻi poʻo pa’ū taimi.

Faʻatasi ai ma fesoʻotaʻiga talafeagai, o le aofaʻi masani o le faʻafesoʻotaʻiga tatau ona faʻamalieina le maualuga maualuga taimi o le ata.

E tatau ona faʻaaoga le soʻotaga o le Edge-couple i le mea e gata ai le mafai ina ia aloese mai le soʻotaga o ulugaliʻi-ulugaliʻi, o le 3S vaevaeina tulafono e tatau ona faʻaaogaina e aloese ai mai le soʻoga faʻatasi poʻo le fetausiaʻi o upu.

(7) Faʻamatalaga e uiga i le faʻamamaina o leo mo le saoasaoa televave sisitema.

Faʻalaʻitiiti le faʻalavelave faʻasolosolo malie (lalo o le 1KHz) mafua mai i le paoa mafuaʻaga paoa, ma faʻaopopo talipupuni poʻo le faʻamamāina matagaluega i pito paoa mana ulufale uma.

Faʻaopopo le 100F electrolytic capacitor filter i nofoaga taʻitasi e ulufale ai le eletise i le PCB.

Ina ia faʻaititia le leo soʻo maualuga, tuʻu le tele o mea puʻe uila i Vcc ma le GND i taimi uma e mafai ai.

Faʻatulaga vaʻavaʻa Vcc ma GND vaʻalele, tuʻueseese i latou ma dielectrics (e pei o FR-4PCB), ma faʻataʻoto bypass capacitors i isi vaega.

(8) Maualuga saosaoa Faʻavaʻa o le Eleele

Taumafai e faʻaopopo se decoupling capacitor i taʻitasi Vcc / GND signal pair.

O se Buffer fafo ua faʻaopopoina i le pito iuga o maualuga-saosaoa suiga suiga faʻailoga e pei o counters e faʻaititia ai le manaʻoga o avetaavale gafatia.

O le Slow Slew (low-rise-slope) mode na seti mo galuega faatino faailo e le manaʻomia se saosaoa saosaoa.

Faʻatonutonu avega avega.

Faʻaititia le uati feliʻu faʻailo, pe tufatufaina ia tutusa i le mafai e faʻataʻamilo ai le malamala.

O le faʻailo e faʻapipiʻi soʻo e latalata lava ile pine ole GND ole avanoa pe a mafai.

O le tisaini o soʻoga taimi faʻasologa tatau ona aloese mai le vave fesuiaʻi o galuega.

Suʻesuʻeina o le paoa sapalai ma le eleele mafai ona faia se sao i le aotelega inductance.