- 18
- Oct
How to avoid PCB design mistakes?
I. Ke kahua hoʻokomo ʻikepili
1. Inā piha nā ʻikepili i loaʻa i ke kaʻina hana (me ke kiʻikuhi hoʻolālā. Faila BRD, papa inoa mea, PCB hoʻolālā kikoʻī a me ka hoʻolālā PCB a i ʻole koi koi e pono ai, hōʻike kikoʻī kaulike a me ke ʻano hoʻolālā hana)
2. E hōʻoia i ka ʻike hou o ka anakuhi PCB
3. Ensure that the positioning components of the template are correctly located
4.PCB design description and PCB design or change requirements, standardization requirements are clear
5. E hōʻoia i ka hāmeʻa ʻia o nā hāmeʻa i pāpā ʻia a me nā wahi pilina ma ke kiʻikuhi outline ma ka anakuhi PCB
6. Hoʻohālikelike i ke kaha kiʻi e hōʻoia i ka pololei o nā ana a me nā ahonui i kau ʻia ma PCB, a pololei ka wehewehe o ka puka metala a me ka puka nonmetalized
7. Ma hope o ka hōʻoiaʻiʻo ʻana i ka pololei o ka anakuhi PCB, ʻoi aku ka maikaʻi o ka laka ʻana i ka faile e neʻe ai i ka neʻe hewa ʻana
ʻO ka lua, ma hope o ka pae nānā ʻōnaehana
A. Nānā i nā ʻāpana
8. E hōʻoia inā kūlike nā pūʻolo lako āpau me ka waihona i hoʻohui ʻia o ka ʻoihana a inā ua hōʻano hou ʻia ka waihona waihona (nānā i nā hopena e holo nei me ka viewlog). Inā ʻaʻole, Hoʻohou i nā Hōʻailona
9, motherboard a me ka papa-papa, ka papa a me ka backboard, e hōʻoia i ke kūlike o ka hōʻailona, ua kūlike ke kūlana, pololei ke kuhikuhi hoʻohui a me ka ʻike pale silika, a he mau anti-misinsertion nā ana o ka papa ma lalo. ʻaʻole pono ka papa sub-a me ka motherboard e hoʻopalai
10. 100% hoʻonoho ʻia nā ʻāpana
11. Open place-bound for the TOP and BOTTOM layers of the device to see if DRC caused by overlap is allowed
12. Inā lawa paha ka māka ʻo Mark
13. E kau ʻia nā mea kaumaha ma kahi kokoke i ke kiko kākoʻo PCB a i ʻole ʻaoʻao kākoʻo e hōʻemi i ka warpage o ka PCB
14. ʻOi aku ka maikaʻi o ka laka ʻana i nā hāmeʻa pili i ka hoʻolālā ma hope o ka hoʻonohonoho ʻia ʻana i mea e pale ai i ka misoperation mai ka neʻe ʻana i ke kūlana
15. Within 5mm around the crimping socket, the front side is not allowed to have components whose height exceeds the height of the crimping socket, and the back side is not allowed to have components or solder joints
16. E hōʻoia inā kū pono ka hoʻolālā ʻōnaehana i nā koi ʻenehana (kālele ana ma ka BGA, PLCC a me ke kahua paʻa)
17, nā ʻāpana pūpala hao, e nānā pono i ka pili ʻole i nā mea ʻē aʻe, e waiho i kahi kūlana kūpono
18. E hoʻokau ʻia nā mea pili i ka ʻaoʻao kokoke i ka interface, a e hoʻokau ʻia ka mea hoʻokele backplane kokoke i ka pūnaewele backplane
19. Inā ua hoʻololi ʻia ka hāmeʻa CHIP ma ka pae soldering nalu i pūʻolo soldering nalu,
20. Whether there are more than 50 manual solder joints
21. Pono e noʻonoʻo pono i ke kau ʻana no ka piʻi axial o nā mea kiʻekiʻe ma PCB. Leave room for sleeping. A noʻonoʻo i ke ʻano paʻa, e like me ke aniani paʻa pale
22. E hōʻoia i ka lawa o ka hoʻokaʻawale ma waena o nā hāmeʻa e hoʻohana ana i ka pale wela a me nā hāmeʻa ʻē aʻe, a hoʻolohe i ke kiʻekiʻe o nā hāmeʻa nui i loko o ka pae o ka wela.
B. Hoʻonohonoho hana
23. Whether the layout of digital circuit and analog circuit components of the digital-analog hybrid board has been separated, and whether the signal flow is reasonable
24, hoʻonoho ʻia nā mea hoʻohuli A / D ma o nā pākana analog.
25, clock device layout is reasonable
26. Whether the layout of high-speed signal devices is reasonable
27, inā ua hoʻonohonoho pono ʻia ka hāmeʻa kikowaena (pono e kau ʻia ke kūʻē i nā kūʻē kūʻē i ka hopena o ka pihi hōʻailona; Hoʻokomo ʻia ke kūʻē kaulike kaulike waena i ke kūlana waena; Pono e kau ʻia i ka hopena hoʻokūkū kūʻē i ka hopena o ka hōʻailona.
28. Inā kūpono ka helu a me kahi o ka decoupling capacitors o nā hāmeʻa IC
29. Lawe nā laina hōʻailona i nā mokulele o nā pae like ʻole e like me nā mokulele kūmole. Ke hele nei i ka ʻāpana i hoʻokaʻawale ʻia e nā mokulele, inā paha ʻo ka capacitance hoʻohui ma waena o nā mokulele kūmole kokoke i ka ʻāpana hoʻoneʻe hōʻailona.
30. Inā kūpono a hoʻonohonoho pono i ka hoʻonohonoho o ka pōʻai pale i ka hoʻokaʻawale ʻana
31. Inā hoʻonoho ʻia ka fuse o ka lako mana o ka papa ma kahi kokoke i ka hoʻopili a ʻaʻohe mea kaapuni i mua o ia
32. E hōʻoia i kēlā hōʻailona ikaika a me nā hōʻailona nāwaliwali (ʻokoʻa mana 30dB) hoʻonohonoho kaʻawale
33. Hoʻonoho ʻia nā hāmeʻa e hoʻopili i nā hoʻokolohua EMC e like me nā kulekele hoʻolālā a i ʻole kuhikuhi i nā hopena kūleʻa. ʻO kahi laʻana: ʻo ke kaapuni hoʻonohonoho o ka panela e kokoke iki i ka pihi hoʻonohonoho
C. wela
34, no nā mea wela wela (me ka capacitance wai waena, ka haʻalulu aniani) a hiki i kahi mamao loa mai nā mea mana kiʻekiʻe, radiator a me nā kumu wela ʻē aʻe
35. Inā kū ka hoʻonohonoho i nā koi o ka hoʻolālā ʻana wela a me nā kahawai hoʻohauna wela (e like me nā palapala hoʻolālā hana)
D. ka mana
36. E hōʻoia inā mamao loa ka lako mana IC mai ka IC
37. Inā kūpono ka hoʻonohonoho ʻana o LDO a me ke kaʻapuni e pili ana
38. Is the circuit layout around the module power supply reasonable
39. Kūpono ka hoʻolālā holoʻokoʻa o ka lako mana
E. Nā Kauoha Rula
40. E hōʻoia inā ua hoʻohui pololei ʻia nā mea hoʻohālikelike a pau i ka Mana Kēpē
41. Ua hoʻonohonoho pololei ʻia nā rula o ke kino a me ka uila (kahakaha nā palena no ka pūnaewele pūnaewele a me ka pūnaewele kahua)
42. Inā lawa paha ka hoʻokaʻawale ma waena o Test Via a me Pin Pin
43. Inā kū ka mānoanoa o ka lamination a me ke kumumanaʻo i ka hoʻolālā a me nā koi e pono ai
44. Inā ua helu ʻia ka impedance o nā laina ʻokoʻa āpau me nā koi impedance ʻano a kāohi ʻia e nā lula