I. Laasaga faʻaulufaleina faʻamatalaga

1. Pe o faʻamatalaga na mauaina i le gaioiga ua maeʻa (e aofia ai le ata faʻafanua. Faila BRD, lisi mea, PCB tisaini faʻapitoa ma PCB tisaini poʻo suiga manaʻoga, faʻamalamalamaina faʻapitoa ma faʻagasologa o tisaini faʻapitoa)

2. Ia mautinoa o le PCB template ua lata mai nei

3. Ensure that the positioning components of the template are correctly located

4.PCB design description and PCB design or change requirements, standardization requirements are clear

5. Faamautinoa o masini faasaina ma vaega o uaea i luga o le outline diagram o loʻo atagia mai i le PCB template

6. Faʻatusatusa le outline ata e faʻamaonia ai o le itu ma tolerances makaina i luga o PCB e saʻo, ma le faʻauiga o uʻamea faʻamauina ma nonmetalized pu e saʻo

7. A maeʻa faʻamaonia le saʻo o le PCB template, e sili le lokaina o le fausaga faila e aloese ai mai le minoi e le misoperation

Lona lua, pe a maeʻa le tulaga siaki siaki

A. Siaki vaega

8. Faʻamaonia pe o mea uma afifi masini e ogatusa ma le tuʻufaʻatasia faletusi o le kamupani ma pe ua faʻafouina le faletusi afifi (siaki le tamoʻe iʻuga ma viewlog). A leai, faʻafouina Faʻailoga

9, motherboard ma sub-board, laupapa ma laupapa i tua, ia mautinoa o le faailo e tutusa, o le tulaga e tutusa, o le fesoʻotaʻiga faʻatonutonu ma silika faʻailoilo screen e saʻo, ma o le sub-laupapa o loʻo i ai anti-misinsertion fua, ma vaega o loʻo i luga le laulau-laupapa ma le motherboard e le tatau ona faʻalavelave

10. Pe o vaega e 100% tuʻuina

11. Open place-bound for the TOP and BOTTOM layers of the device to see if DRC caused by overlap is allowed

12. Pe o le maka Mark e lava ma talafeagai

13. O vaega mamafa e tatau ona tuʻu latalata i le lagolago a le PCB poʻo le itu lagolago e faʻaititia ai le taua o le PCB

14. E sili ona lelei le lokaina ole masini-fesoʻotaʻi masini pe a uma ona faʻatulagaina ina ia puipuia ai le faʻagaioiga sese mai le minoiina o le tulaga

15. Within 5mm around the crimping socket, the front side is not allowed to have components whose height exceeds the height of the crimping socket, and the back side is not allowed to have components or solder joints

16. Faʻamaonia pe o le masini faʻatulagaina faʻamalieina tekinolosi manaʻoga (taulaʻi ile BGA, PLCC ma patch mataʻupu)

17, uʻamea atigi vaega, totino faʻapitoa mafaufau e le fetoʻi ma isi vaega, e tuua lava avanoa avanoa

18. O mea e fesoʻotaʻi i luga ole laʻau e tatau ona tuʻu latalata i le interface, ma le pasi pasi pasi e tatau ona tuʻu latalata i le backplane connector

19. Pe o le masini CHIP luga o le galu soldering luga ua uma ona liua i galu soldering afifi,

20. Whether there are more than 50 manual solder joints

21. Faʻaputuga faʻapipiʻi tatau ona iloiloina mo axial faʻaputuga o maualuga vaega i PCB. Leave room for sleeping. Ma mafaufau i le faʻavasega auala, pei o tioata faʻamau pad

22. Faʻamautinoa o loʻo lava le va i le va o masini e faʻaaogaina le vevela tapu ma isi masini, ma faʻalogo i le maualuga o masini autu i totonu o le vevela sink range

B. Siaki galuega

23. Whether the layout of digital circuit and analog circuit components of the digital-analog hybrid board has been separated, and whether the signal flow is reasonable

24, A / D liliu mai o loʻo tuʻu faʻasolosolo i vavaega analog.

25, clock device layout is reasonable

26. Pe o le faʻatulagaina o televave faʻailo masini e talafeagai

27, pe o le masini masini na faʻatulagaina lelei (mafuaʻaga tutusa faʻasologa teteʻe tatau ona tuʻuina i le faʻailoga o le drive end; O le ogatotonu faʻafetauiina manoa teteʻe ua tuʻuina i le ogatotonu tulaga; Tigaina fetaui faʻasologa teteʻe tatau ona tuʻuina i le mauaina faʻaiuga o le faʻailoga)

28. Pe o le numera ma le nofoaga o decoupling capacitors o IC masini e talafeagai

29. O laina faʻailo e ave vaʻalele o tulaga eseʻese e pei o vaʻalele vaʻai. Pe a sopoia le itulagi vaeluaina e vaalele, pe o le fesoʻotaʻi capacitance i le va o vaʻavaʻa vaʻalele e latalata i le faʻailoga ala faʻasolosolo itulagi.

30. Pe o le faʻatulagaina o le puipuiga matagaluega e talafeagai ma fesoasoani i vaevaega

31. Pe o le fuse o le paoa sapalai o le laupapa e tu latalata i le fesoʻotaʻiga ma e leai se vaega matagaluega i ona luma

32. Faʻamaonia o le malosi faʻailo ma vaivaiga faʻailo (mana eseesega 30dB) liʻo ua faʻatulaga eseese

33. Pe o masini e ono aʻafia ai faʻataʻitaʻiga a le EMC e tuʻuina atu e tusa ai ma taʻiala o faʻataʻitaʻiga poʻo le faʻasino i mea lelei na tutupu. Mo se faʻataʻitaʻiga: o le toe faʻamavaeina o le laulau e tatau ona fai si latalata i le toe setiina

Fiva

34, mo vevela vevela vaega (aofia ai suavai auala capacitance, tioata gatete) i le mamao e mafai ese mai maualuga-mana vaega, radiator ma isi vevela mafuaʻaga

35. Pe o le faʻataʻitaʻiga e faʻamalieina manaʻoga o le vevela mamanu ma vevela faʻaseseina auala (e tusa ai ma le gaioiga faʻamaumauga pepa)

D. le malosiʻaga

36. Siaki pe o le IC eletise sapalai e mamao tele mai le IC

37. Pe o le faʻatulagaina ole LDO ma faʻataʻamilosaga lata mai e talafeagai

38. Is the circuit layout around the module power supply reasonable

39. E talafeagai le faʻatulagaina lautele o le paoa sapalai

E. Tulafono faatulagaga

40. Siaki pe o faʻataʻitaʻiga faʻataʻitaʻi uma na sao ona faʻaopopoina i le Pule o le Faʻafeaa

41. O tulafono faʻaletino ma eletise faʻatulagaina saʻo (tusi faʻatapulaʻa setiina mo le malosiaga fesoʻotaʻiga ma eleele fesoʻotaʻiga)

42. Pe o le va i le va o le Test Via ma le Test Pin ua lava lea

43. Pe o le mafiafia o le lamination ma le polokalame faʻamalieina le mamanu ma gaioiga manaʻoga

44. Pe o le faʻafitauli o laina eseʻese uma ma uiga manaʻomia impedance ua uma ona fuafuaina ma faʻatautaia e tulafono