The increasing complexity of PCB design considerations, such as clock, cross talk, impedance, detection, and manufacturing processes, often forces designers to repeat a lot of layout, verification, and maintenance work. The parameter constraint editor codifies these parameters into formulas to help designers better deal with these sometimes contradictory parameters during design and production.

In recent years, PCB layout and routing requirements have become more complex, and the number of transistors in integrated circuits has increased as predicted by Moore’s Law, making devices faster and each pulse shorter along the rise time, as well as increasing the number of pins — often 500 to 2,000. All of this creates density, clock, and crosstalk problems when designing a PCB.

A few years ago, most PCBS had only a handful of “critical” nodes (Nets), typically defined as constraints on impedance, length, and clearance. PCB designers would manually route these routes and then use software to automate large-scale routing of the entire circuit. Today’s PCBS often have 5,000 or more nodes, more than 50% of which are critical. Due to the time to market pressure, manual wiring is not possible at this point. Moreover, not only has the number of critical nodes increased, but the constraints on each node have also increased.

These constraints are mainly due to the correlation parameters and design requirements of more and more complex, for example, the two linear interval may depend on an and node voltage and circuit board materials are related functions, digital IC rise time decreases of high speed and low clock speed can influence the design, due to pulse faster and to establish and maintain a shorter time, In addition, as an important part of the total delay of high-speed circuit design, interconnect delay is also very important for low-speed design.

Some of these problems would be easier to solve if boards were bigger, but the trend is in the opposite direction. Due to the requirements of interconnect delay and high density package, the circuit board is becoming smaller and smaller, so high density circuit design appears, and miniaturization design rules must be followed. Reduced rise times combined with these miniaturized design rules make crosstalk noise an increasingly prominent problem, and ball grid arrays and other high-density packages themselves exacerbate crosstalk, switching noise, and ground bounce.

Fixed constraints that exist

The traditional approach to these problems is to translate electrical and process requirements into fixed constraint parameters by experience, default values, number tables, or calculation methods. For example, an engineer designing a circuit may first determine a rated impedance and then “estimate” a rated line width to achieve the desired impedance based on the final process requirements, or use a calculation table or arithmetic program to test for interference and then work out the length constraints.

This approach typically requires a set of empirical data to be designed as a basic guideline for PCB designers so that they can leverage this data when designing with automatic layout and routing tools. The problem with this approach is that empirical data is a general principle, and most of the time they are correct, but sometimes they don’t work or lead to wrong results.

Let’s use the example of determining impedance above to see the error this method can cause. Factors related to impedance include the dielectric properties of the board material, the height of the copper foil, the distance between the layers and the ground/power layer, and the line width. Since the first three parameters are generally determined by the production process, designers usually use line width to control impedance. Since the distance from each line layer to the ground or power layer is different, it is clearly a mistake to use the same empirical data for each layer. This is compounded by the fact that the manufacturing process or circuit board characteristics used during development can change at any time.

Most of the time these problems will be exposed in the prototype production stage, the general is to find out the problem through the circuit board repair or redesign to solve the board design. The cost of doing so is high, and fixes often create additional problems that require further debugging, and the loss of revenue due to delayed time to market far exceeds the cost of debugging.Almost every electronics manufacturer faces this problem, which ultimately boils down to the inability of traditional PCB design software to keep up with the realities of current electrical performance requirements. It is not as simple as empirical data on mechanical design.

What can be used to constrain PCB design?

Solution: Parameterize constraints

At present design software vendors try to solve this problem by adding parameters to constraints. The most advanced aspect of this approach is the ability to specify mechanical specifications that fully reflect various internal electrical characteristics. Once these are incorporated into the PCB design, the design software can use this information to control the automatic layout and routing tool.

When the subsequent production process changes, there is no need to redesign. The designers simply update the process characteristic parameters, and the relevant constraints can be changed automatically. The designer can then run DRC (Design Rule Check) to determine if the new process violates any other design rules and to find out what aspects of the design should be changed to correct all errors.

Constraints can be input in the form of mathematical expressions, including constants, various operators, vectors, and other design constraints, providing designers with a parameterized rule-driven system. Constraints can even be entered as look-up tables, stored in a design file on a PCB or schematic. PCB wiring, copper foil area location, and layout tools follow the constraints generated by these conditions, and DRC verifies that the entire design complies with these constraints, including line width, spacing, and space requirements such as area and height restrictions.

Hierarchical management

One of the main benefits of parameterized constraints is that they can be graded. For example, the global line width rule can be used as a design constraint in the whole design. Of course, some regions or nodes cannot copy this principle, so the higher-level constraint can be bypassed and the lower-level constraint in the hierarchical design can be adopted. Parametric Constraint Solver, A Constraint editor from ACCEL Technologies, is given a total of 7 levels:

1. Design constraints for all objects that have no other constraints.

2. Hierarchy constraints, applied to objects at a certain level.

3. Node type constraint applies to all nodes of a certain type.

4. Node constraint: applies to a node.

5. Inter-class constraint: indicates the constraint between nodes of two classes.

6. Spatial constraint, applied to all devices in a space.

7. Device constraints, applied to a single device.

The software follows various design constraints from individual devices to the whole design rules, and shows the application order of these rules in the design by way of graphics.

Example 1: Line width = F (impedance, layer spacing, dielectric constant, copper foil height). Here is an example of how parameterized constraints can be used as design rules to control impedance. As mentioned above, impedance is a function of dielectric constant, distance to the nearest line layer, width and height of copper wire. Since the impedance required by design has been determined, these four parameters can be arbitrarily taken as relevant variables to rewrite the impedance formula. In most cases, designers can control only line width.

Because of this, the constraints on line width are functions of impedance, dielectric constant, distance to the nearest line layer, and height of the copper foil. If the formula is defined as a hierarchical constraint and the manufacturing process parameters as a design-level constraint, the software will automatically adjust the line width to compensate when the designed line layer changes. Similarly, if the designed circuit board is produced in a different process and the copper foil height is changed, the relevant rules in the design level can be recalculated automatically by changing the copper foil height parameters.

Example 2: Device interval = Max (default interval, F (device height, detection Angle).The obvious benefit of using both parameter constraints and design rule checking is that the parameterized approach is portable and monitored when design changes occur. This example shows how device spacing can be determined by process characteristics and test requirements. The formula above shows that device spacing is a function of device height and detection Angle.

The detection Angle is usually a constant for the entire board, so it can be defined at the design level. When checking on a different machine, the entire design can be updated simply by entering new values at the design level. After the new machine performance parameters are entered, the designer can know whether the design is feasible by simply running the DRC to check whether the device spacing conflicts with the new spacing value, which is much easier than analyzing, correcting and then making hard calculations according to the new spacing requirements.

What can be used to constrain PCB design?

Example 3: Component layout,In addition to organizing design objects and constraints, design rules can also be used for component layout, that is, it can detect where to place devices without causing errors based on constraints. Highlighted in figure 1 is to meet physical constraints (such as interval and the edge of the plate spacing and device) devices place area, figure 2 highlights is to meet the electrical constrained device placement areas, such as maximum line length, figure 3 shows only the area of space constraint, finally, figure 4 is the intersection of the first three parts of the picture, this is the effective area layout, Devices placed in this region can satisfy all constraints.

What can be used to constrain PCB design？

In fact, generating constraints in a modular manner can greatly improve their maintainability and reusability. New expressions can be generated by referring to the constraint parameters of different layers in the previous stage, for example, the line width of the top layer depends on the distance of the top layer and the height of the copper wire, and the variables Temp and Diel_Const in the design level. Note that design rules are displayed in descending order, and changing a higher-level constraint immediately affects all expressions that refer to that constraint.

What can be used to constrain PCB design？

Design reuse and documentation

Parametric constraints, not only can significantly improve the initial design process, and reuse of engineering change and design more useful, the constraint can be used as part of the design, system and documents, if not only in engineer or designer’s mind, so when they turn to other projects may be slowly forget. Constraint documents document the electrical performance rules to be followed during the design process and provide an opportunity for others to understand the designer’s intentions so that these rules can be easily applied to new manufacturing processes or changed according to electrical performance requirements. Future multiplexers can also know the exact design rules and make changes by entering new process requirements without having to guess how line widths were obtained.

This article conclusion

The parameter constraint editor facilitates PCB layout and routing under multi-dimensional constraints, and for the first time enables automatic routing software and design rules to be fully checked against complex electrical and process requirements, rather than just relying on experience or simple design rules that are of little use. The result is a design that can achieve a one-time success, reducing or even eliminating prototype debugging.