ʻO ka hoʻonui ʻana i ka paʻakikī o PCB design considerations, such as clock, cross talk, impedance, detection, and manufacturing processes, often forces designers to repeat a lot of layout, verification, and maintenance work. Kuhi ka mea hoʻoponopono palena palena palena palena i kēia mau palena i nā ʻano hana e kōkua i nā mea hoʻolālā e hana maikaʻi me kēia mau manawa kūʻē i ka hoʻolālā a me ka hana.

I nā makahiki i hala aku nei, ua lilo ka hoʻonohonoho PCB a me nā koina hoʻokele i mea paʻakikī, a ua hoʻonui ka nui o nā transistors i nā kaapuni hoʻohui e like me ka mea i wānana ʻia e ke kānāwai o Moore, e wikiwiki ana i nā hāmeʻa a ʻoi aku ka pōkole o kēlā me kēia pā i ka manawa piʻi, a me ka hoʻonui ʻana i ka nui o nā pine – pinepine 500 a 2,000. Hana kēia mau mea āpau i nā pilikia nui, uaki, a me crosstalk ke hoʻolālā ʻana i kahi PCB.

I kekahi mau makahiki i hala aku nei, ʻo ka hapa nui o PCBS he ʻāpana wale nō o nā node “kūpilikiʻi” (Nets), i wehewehe pinepine ʻia e like me nā kaohi o ka impedance, ka lōʻihi, a me ka ʻae. E hana lima nā mea hoʻolālā PCB i kēia mau ala a laila hoʻohana i ka polokalamu e hana maʻalahi i ka hoʻoneʻe nui ʻana o ke kaapuni holoʻokoʻa. Loaʻa nā PCBS o kēia lā he 5,000 a ʻoi paha nā aka, ʻoi aku ma mua o 50% o ia mau mea koʻikoʻi. Due to the time to market pressure, manual wiring is not possible at this point. Moreover, not only has the number of critical nodes increased, but the constraints on each node have also increased.

These constraints are mainly due to the correlation parameters and design requirements of more and more complex, for example, the two linear interval may depend on an and node voltage and circuit board materials are related functions, digital IC rise time decreases of high speed and low clock speed can influence the design, due to pulse faster and to establish and maintain a shorter time, In addition, as an important part of the total delay of high-speed circuit design, interconnect delay is also very important for low-speed design.

ʻOi aku ka maʻalahi o kekahi o kēia mau pilikia e hoʻonā inā ʻoi aku ka nui o nā papa, akā aia ke ʻano i ka ʻaoʻao ʻē aʻe. Ma muli o nā koi o ka lohi interconnect a me ka pūʻolo kiʻekiʻena kiʻekiʻe, e liʻiliʻi ana ka liʻiliʻi a me ka liʻiliʻi o ka papa kaapuni, no laila ʻike ʻia ka hoʻolālā kaapuni kiʻekiʻe, a pono e ukali i nā lula hoʻolālā miniaturization. Reduced rise times combined with these miniaturized design rules make crosstalk noise an increasingly prominent problem, and ball grid arrays and other high-density packages themselves exacerbate crosstalk, switching noise, and ground bounce.

Nā mea paʻa paʻa e kū nei

ʻO ke kuʻuna kuʻuna i kēia mau pilikia e unuhi i nā pono uila a me nā kaʻina hana i nā palena palena paʻa e ka ʻike, nā helu paʻamau, nā papa helu, a me nā ʻano helu. ʻO kahi laʻana, hiki i kahi ʻenekini ke hoʻolālā i kahi kaapuni ke hoʻoholo mua i kahi impedance i helu ʻia a laila “koho” i ka laulā laina i helu ʻia e hoʻokō i ka impedance i makemake ʻia e pili ana i nā koi o ka hana hope loa, a i ʻole hoʻohana i ka papa helu helu a i ʻole papahana arithmetic e hoʻāʻo ai no ka hihia a laila hana. mai nā kaohi o ka lōʻihi.

This approach typically requires a set of empirical data to be designed as a basic guideline for PCB designers so that they can leverage this data when designing with automatic layout and routing tools. ʻO ka pilikia me kēia ala, ʻo ia ka ʻike empirical i kumu nui, a ʻo ka hapa nui o ka manawa pololei, akā ʻaʻole hana kekahi manawa a alakaʻi ʻole i nā hopena hewa.

E hoʻohana i ka laʻana o ka hoʻoholo ʻana i ka impedance ma luna e ʻike i ka hemahema o kēia hana. ʻO nā kumu e pili ana i ka impedance me nā waiwai dielectric o ka papa, ke kiʻekiʻe o ka pepa keleawe, ka mamao ma waena o nā papa a me ka papa honua / mana, a me ka laulā o ka laina. Ma muli o ka hoʻoholo mua ʻia o nā pae mua ʻekolu e ke kaʻina hana, hoʻohana pinepine nā mea hoʻolālā i ka laulā laina e kāohi i ka impedance. Since the distance from each line layer to the ground or power layer is different, it is clearly a mistake to use the same empirical data for each layer. This is compounded by the fact that the manufacturing process or circuit board characteristics used during development can change at any time.

ʻO ka hapanui o ka manawa e hōʻike ʻia kēia mau pilikia i ka pae hana prototype, ʻo ka mea maʻamau ka ʻike i ka pilikia ma o ka hoʻoponopono ʻana o ka papa kaapuni a i ʻole hana hou ʻana e hoʻonā i ka hoʻolālā papa. The cost of doing so is high, and fixes often create additional problems that require further debugging, and the loss of revenue due to delayed time to market far exceeds the cost of debugging.Almost every electronics manufacturer faces this problem, which ultimately boils down to the inability of traditional PCB design software to keep up with the realities of current electrical performance requirements. It is not as simple as empirical data on mechanical design.

He aha ka mea e hiki ke hoʻohana ʻia e kāohi i ka hoʻolālā PCB?

Pāʻoihana: Parameterize kaohi

I kēia manawa e hoʻāʻo nā mea kūʻai lako polokalamu hoʻolālā e hoʻoponopono i kēia pilikia ma ka hoʻohui ʻana i nā palena i nā kaohi. ʻO ka hiʻohiʻona kiʻekiʻe loa o kēia ala ke hiki ke kuhikuhi i nā kikoʻī mechanical e hōʻike piha i nā ʻano uila o loko. Ke hoʻohui ʻia kēia mau mea i loko o ka hoʻolālā PCB, hiki i ka lako polokalamu hoʻolālā ke hoʻohana i kēia ʻike e kaohi ai i ka hoʻonohonoho aunoa a me ka pono hana.

When the subsequent production process changes, there is no need to redesign. The designers simply update the process characteristic parameters, and the relevant constraints can be changed automatically. Hiki i ka mea hoʻolālā ke holo iā DRC (Design Rule Check) e hoʻoholo inā e hōʻeha ke kaʻina hana hou i nā lula hoʻolālā ʻē aʻe a e ʻike i nā ʻāpana o ka hoʻolālā e hoʻoponopono e hoʻoponopono i nā hewa āpau.

Hiki ke hoʻokomo ʻia nā mea kāohi i ke ʻano o nā huaʻōlelo makemakika, e like me nā paʻa, nā mea lawelawe like ʻole, nā vector, a me nā kaohi hoʻolālā ʻē aʻe, e hāʻawi ana i nā mea hoʻolālā me kahi ʻōnaehana i hoʻokau ʻia e ka lula. Constraints can even be entered as look-up tables, stored in a design file on a PCB or schematic. ʻO ka hoʻopili ʻana o PCB, kahi o ka wahi keleawe, a me nā pono hoʻonohonoho e ukali i nā kaohi i hoʻokumu ʻia e kēia mau ʻano, a hōʻoia ʻo DRC e pili ana ka hoʻolālā holoʻokoʻa i kēia mau kaohi, e like me ka laulā laina, ka spacing, a me nā koi ākea e like me nā palena o ka palena a me ke kiʻekiʻe.

Harkarchical hoʻokele

ʻO kekahi o nā pōmaikaʻi nui o nā kaohi palena ʻia ʻo ia ka hiki ke koho ʻia. ʻO kahi laʻana, hiki ke hoʻohana ʻia ka lula ākea laina laulā ma ke ʻano he kaohi hoʻolālā i ka hoʻolālā holoʻokoʻa. ʻOiaʻiʻo, ʻaʻole hiki i kekahi mau wahi a i ʻole nā ​​pona ke kope i kēia loina, no laila hiki ke kāpae ʻia i ka palena kiʻekiʻe loa a hiki ke ʻae ʻia ka palena haʻahaʻa haʻahaʻa i ka hoʻolālā hierarchical. Hāʻawi ʻia ʻo Parametric Constraint Solver, kahi mea hoʻoponopono Constraint mai ACCEL Technologies, i nā pae he 7:

1. E hoʻolālā i nā kaohi no nā mea āpau i loaʻa ʻole nā ​​kaohi ʻē aʻe.

2. Nā pilikia Hierarchy, hoʻopili ʻia i nā mea i kekahi pae.

3. Pili ka palena o ke ʻano node i nā aka āpau o kekahi ʻano.

4. Node constraint: applies to a node.

5. Kaohi waena o ka papa: hōʻike i ka palena ma waena o nā aka o nā papa ʻelua.

6. Spatial constraint, applied to all devices in a space.

7. Kaohi mea, hoʻopili ʻia i hoʻokahi hāmeʻa.

Hāpai ka polokalamu i nā kaohi hoʻolālā like ʻole mai kēlā me kēia hāmeʻa i nā lula hoʻolālā holoʻokoʻa, a hōʻike i ke kaʻina noi o kēia mau lula i ka hoʻolālā ma o nā kiʻi.

Example 1: Line width = F (impedance, layer spacing, dielectric constant, copper foil height). Eia kahi laʻana pehea e hiki ai ke hoʻohana ʻia nā palena palena palena paramed e like me nā lula hoʻolālā e kāohi i ka impedance. E like me ka mea i ʻōlelo ʻia ma luna, ʻo ka impedance kahi hana o ka dielectric mau, kahi mamao i ka papa laina kokoke, ka laulā a me ke kiʻekiʻe o ka uea keleawe. Ma muli o ka hoʻoholo ʻana o ka impedance e ka hoʻolālā, hiki ke lawe ʻia kēia mau palena ʻehā i mau ʻano pili kūpono e kākau hou i ka hana impedance. I ka hapanui o nā hihia, hiki i nā mea hoʻolālā ke kāohi i ka laulā laina wale nō.

Because of this, the constraints on line width are functions of impedance, dielectric constant, distance to the nearest line layer, and height of the copper foil. Inā wehewehe ʻia ke kumumanaʻo ma ke ʻano he hierarchical constraint a me nā kaʻina hana o ka hana ʻana ma ke ʻano he palena pae hoʻolālā, e hoʻomaʻa aunoa ka polokalamu i ka laulā laina e uku i ka loli ʻana o ka papa laina i hoʻolālā ʻia. Pēlā nō, inā hana ʻia ka papa kaapuni i hoʻolālā ʻia i kahi hana ʻokoʻa a hoʻololi ʻia ke kiʻekiʻe o ke keleawe, hiki ke helu hou ʻia nā lula pili i ka pae hoʻolālā e ka hoʻololi ʻana i nā palena kiʻekiʻe o ke keleawe.

Example 2: Device interval = Max (default interval, F (device height, detection Angle).ʻO ka pōmaikaʻi maopopo o ka hoʻohana ʻana i nā palena palena o ka ʻelua a me ka nānā ʻana i nā lula hoʻolālā ʻo ia ke ʻano parameterized i lawe ʻia a nānā ʻia ke hoʻololi ʻia nā hoʻolālā. This example shows how device spacing can be determined by process characteristics and test requirements. The formula above shows that device spacing is a function of device height and detection Angle.

ʻO ka Angle ʻike he mea mau ia no ka papa holoʻokoʻa, no laila hiki ke wehewehe ʻia i ka pae hoʻolālā. Ke nānā nei i kahi mīkini ʻokoʻa, hiki ke hoʻohou i ka hoʻolālā holoʻokoʻa ma ke komo ʻana i nā waiwai hou i ka pae hoʻolālā. Ma hope o ke komo ʻana o nā palena hana mīkini hou, hiki i ka mea hoʻolālā ke ʻike inā hiki ke hoʻolālā ʻia ma o ka holo ʻana i DRC wale nō e nānā inā e hakakā ana ka mokulele me ka waiwai spacing hou, ʻoi aku ka maʻalahi ma mua o ke kālailai ʻana, hoʻoponopono ʻana a laila hana i nā helu paʻakikī e like me i nā koi spacing hou.

He aha ka mea e hiki ke hoʻohana ʻia e kāohi i ka hoʻolālā PCB?

Eia 3: Hoʻonohonoho hoʻonohonoho,Ma waho aʻe o ka hoʻonohonoho ʻana i nā mea hoʻolālā a me nā kaohi, hiki ke hoʻohana ʻia nā lula hoʻolālā no ka hoʻonohonoho ʻana i nā mea, ʻo ia hoʻi, hiki iā ia ke ʻike i kahi e waiho ai i nā hāmeʻa me ka ʻole o nā hemahema e pili ana i nā kaohi. Kahiāuli ʻia i ke kiʻi 1 e kū i nā kaohi o ke kino (e like me ke kowa a me ke kaʻe o ka pā o ka pā a me ka hāmeʻa) kahi o nā hāmeʻa, ʻo ka helu 2 kahi mea e hālāwai ai me nā wahi hoʻonohonoho hoʻonohonoho uila i hoʻopili ʻia, e like me ka lōʻihi o ka laina, hōʻike ka helu 3 wale nō. ʻo ka ʻāpana o ke kaohi ākea, ʻo ka hopena, ʻo ka helu 4 ka intersect o nā ʻekolu mau ʻāpana o ke kiʻi, ʻo kēia kahi hoʻonohonoho kūpono. Devices placed in this region can satisfy all constraints.

What can be used to constrain PCB design？

I ka ʻoiaʻiʻo, ʻo ka hoʻokumu ʻana i nā kaohi i ke ʻano modular hiki ke hoʻomaikaʻi nui i kā lākou paʻa a me ka hoʻohana hou ʻana. New expressions can be generated by referring to the constraint parameters of different layers in the previous stage, for example, the line width of the top layer depends on the distance of the top layer and the height of the copper wire, and the variables Temp and Diel_Const in the design level. Note that design rules are displayed in descending order, and changing a higher-level constraint immediately affects all expressions that refer to that constraint.

What can be used to constrain PCB design？

Hoʻohana hou a hoʻolālā i ka hoʻolālā

Parametric constraints, not only can significantly improve the initial design process, and reuse of engineering change and design more useful, the constraint can be used as part of the design, system and documents, if not only in engineer or designer’s mind, so when they turn to other projects may be slowly forget. Palapala nā palapala kaohi i nā lula hana uila e ukali ʻia i ka wā o ka hoʻolālā a hāʻawi i kahi manawa no nā poʻe ʻē aʻe e maopopo ai i ka manaʻo o ka mea hoʻolālā i hiki ai ke hoʻohana maʻalahi ʻia kēia mau lula i nā kaʻina hana hou a i hoʻololi ʻia paha e like me nā koina hana uila. Future multiplexers can also know the exact design rules and make changes by entering new process requirements without having to guess how line widths were obtained.

This article conclusion

Hoʻonohonoho ka mea hoʻoponopono palena palena i ka hoʻolālā PCB a me ka hoʻokele ma lalo o nā palena maha-dimensional, a no ka manawa mua e hiki ai ke nānā pono i nā lako uila a me nā lula hoʻolālā e nānā kūʻē i nā pono uila a me nā kaʻina hana, ma mua o ka hilinaʻi wale ʻana i ka ʻike a i ʻole nā ​​lula hoʻolālā maʻalahi. hoʻohana liʻiliʻi. The result is a design that can achieve a one-time success, reducing or even eliminating prototype debugging.