Ubunzima obandayo be PCB design considerations, such as clock, cross talk, impedance, detection, and manufacturing processes, often forces designers to repeat a lot of layout, verification, and maintenance work. Umhleli wesithintelo separameter udibanisa ezi paramitha kwiifomula ukunceda abayili bayo bajongane ngcono nezinye iiparitha eziphikisanayo ngexesha loyilo kunye nemveliso.

Kwiminyaka yakutshanje, ubume bePCB kunye neemfuno zendlela ziye zanzima ngakumbi, kwaye inani leetransistors kwiisekethi ezihlanganisiweyo lenyukile njengoko bekuxelwe kwangaphambili nguMthetho kaMorey, zisenza izixhobo zikhawuleze kwaye ukubetha okufutshane kufutshane ngexesha lokunyuka, kunye nokunyusa inani lezikhonkwane. – rhoqo ngama-500 ukuya kuma-2,000 XNUMX. Konke oku kudala uxinano, iwotshi, kunye neengxaki ze-crosstalk xa kuyilwa i-PCB.

Kwiminyaka embalwa edlulileyo, uninzi lwee-PCBS zazinee-node (ezibaluleke kakhulu) (iiNets), ezichazwe njengemiqobo kuthintelo, kubude, nakwimvume. Abaqulunqi be-PCB babeza kuzihambisa ngesandla ezi ndlela emva koko basebenzise isoftware ukwenza umzila omkhulu wesekethe yonke. Ii-PCBS zanamhlanje zihlala zine-5,000 okanye nangaphezulu, ngaphezulu kwe-50% yazo ibaluleke kakhulu. Due to the time to market pressure, manual wiring is not possible at this point. Moreover, not only has the number of critical nodes increased, but the constraints on each node have also increased.

These constraints are mainly due to the correlation parameters and design requirements of more and more complex, for example, the two linear interval may depend on an and node voltage and circuit board materials are related functions, digital IC rise time decreases of high speed and low clock speed can influence the design, due to pulse faster and to establish and maintain a shorter time, In addition, as an important part of the total delay of high-speed circuit design, interconnect delay is also very important for low-speed design.

Ezinye zezi ngxaki bezinokuba lula ukusombulula ukuba iibhodi bezinkulu, kodwa imeko ikwelinye icala. Ngenxa yeemfuno zokulibaziseka kokunxibelelana kunye nephakheji yokuxinana okuphezulu, ibhodi yesekethe iya isiba ncinane kwaye incinci, ke kuyilo oluphezulu lokuxinana kwesekethe liyavela, kunye nemigaqo yoyilo lwe-miniaturization kufuneka ilandelwe. Reduced rise times combined with these miniaturized design rules make crosstalk noise an increasingly prominent problem, and ball grid arrays and other high-density packages themselves exacerbate crosstalk, switching noise, and ground bounce.

Izithintelo ezizinzileyo ezikhoyo

Indlela yesiNtu kwezi ngxaki kukuguqula umbane kunye nenkqubo yeemfuno zenkqubo engqingqwa ngamava, amaxabiso asisiseko, iitafile zamanani, okanye iindlela zokubala. Umzekelo, injineli eyila isekethe inokuthi kuqala igqibe ngesithintelo esilinganisiweyo kwaye emva koko “iqikelele” ububanzi bomgca obekiweyo ukufezekisa i-impedance oyifunayo esekwe kwiimfuno zokugqibela zenkqubo, okanye usebenzise itafile yokubala okanye inkqubo ye-arithmetic ukuvavanya ukuphazamiseka emva koko usebenze ngaphandle kwezithintelo zobude.

This approach typically requires a set of empirical data to be designed as a basic guideline for PCB designers so that they can leverage this data when designing with automatic layout and routing tools. Ingxaki ngale ndlela kukuba idatha ye-empirical ngumgaqo oqhelekileyo, kwaye uninzi lwamaxesha zichanekile, kodwa ngamanye amaxesha azisebenzi okanye zikhokelele kwiziphumo ezingalunganga.

Masisebenzise umzekelo wokumisela i-impedance apha ngasentla ukubona impazamo kule ndlela inokubangela. Izinto ezinxulumene ne-impedance zibandakanya iipropathi ze-dielectric zezinto zebhodi, ukuphakama kwefoyile yobhedu, umgama phakathi konwebu kunye nomaleko womhlaba / wamandla, kunye nobubanzi bomgca. Kuba iiparameter ezintathu zokuqala zihlala zimiselwe yinkqubo yemveliso, abaqulunqi bahlala basebenzisa ububanzi bomgca ukulawula i-impedance. Since the distance from each line layer to the ground or power layer is different, it is clearly a mistake to use the same empirical data for each layer. This is compounded by the fact that the manufacturing process or circuit board characteristics used during development can change at any time.

Amaxesha amaninzi ezi ngxaki ziya kutyhilwa kwinqanaba lemveliso yohlobo lweprototype, ngokubanzi kukufumanisa ingxaki ngokulungiswa kwebhodi yesekethe okanye ukuyila ngokutsha ukusombulula uyilo lwebhodi. Iindleko zokwenza njalo ziphezulu, kwaye izilungiso zihlala zenza iingxaki ezongezelelweyo ezifuna ukuqhubeka nokulungisa ingxaki, kunye nelahleko yengeniso ngenxa yexesha lokulibaziseka lokuthengisa kakhulu kunexabiso lokulungisa.Almost every electronics manufacturer faces this problem, which ultimately boils down to the inability of traditional PCB design software to keep up with the realities of current electrical performance requirements. It is not as simple as empirical data on mechanical design.

Yintoni enokusetyenziselwa ukunyanzela uyilo lwePCB?

Isisombululo: Parameterize iingxaki

Okwangoku abathengisi besoftware yoyilo bazama ukusombulula le ngxaki ngokongeza iiparameter kwizithintelo. Eyona nto iphambili kule ndlela kukukwazi ukucacisa ukubalulwa kwemitshini ebonisa ngokupheleleyo iimpawu zombane zangaphakathi. Nje ukuba ezi zinto zibandakanywe kuyilo lwePCB, isoftware yoyilo inokusebenzisa olu lwazi ukulawula ubeko oluzenzekelayo kunye nesixhobo sokuhambisa.

When the subsequent production process changes, there is no need to redesign. The designers simply update the process characteristic parameters, and the relevant constraints can be changed automatically. Umyili unokuqhuba i-DRC (Jonga uMgaqo woYilo) ukumisela ukuba inkqubo entsha iyaphula nayiphi na eminye imithetho yoyilo kunye nokufumanisa ukuba yeyiphi imiba yoyilo ekufuneka itshintshiwe ukulungisa zonke iimpazamo.

Izithintelo zinokuba negalelo ngohlobo lweentetho zemathematika, kubandakanya ukungqinisisa, abaqhubi abahlukeneyo, iivenkile, kunye nezinye izithintelo zoyilo, ukubonelela abayili ngenkqubo eqhutywa ngumgaqo. Constraints can even be entered as look-up tables, stored in a design file on a PCB or schematic. I-wiring ye-PCB, indawo ye-foil yendawo, kunye nezixhobo zokuyila zilandela imiqobo eveliswe yile miqathango, kwaye i-DRC iqinisekisa ukuba uyilo lonke luyahambelana nale miqobo, kubandakanya ububanzi bomgca, isithuba, kunye neemfuno zesithuba ezinje ngezithintelo zommandla nokuphakama.

Ulawulo lwemigangatho

Esinye sezibonelelo eziphambili zezithintelo zeparameter kukuba zinokuhlelwa. Umzekelo, umthetho wobubanzi bomgca wehlabathi unokusetyenziswa njengesithintelo kuyilo kuyo yonke uyilo. Ewe, eminye imimandla okanye iindawo ezingenakukwazi ukukopa lo mgaqo, ngenxa yoko inyanzelo yenqanaba eliphezulu inokugqitha kunye nesithintelo esikwinqanaba elisezantsi kuyilo lolawulo olunokwamkelwa. IParametric Constraint Solver, Umhleli wesithintelo ovela kwi-ACCEL Technologies, unikwa amanqanaba e-7 ewonke:

1. Izithintelo zoyilo lwazo zonke izinto ezingenazo ezinye iingxaki.

2. Izithintelo zolawulo oluphezulu, ezisetyenziswa kwizinto ezikwinqanaba elithile.

3. Uhlobo lwesithintelo sohlobo lusebenza kuzo zonke iindawo zohlobo oluthile.

4. Node constraint: applies to a node.

5. Ukunqongophala phakathi kodidi: kubonisa isinyanzelo phakathi kweendawo zeeklasi ezimbini.

6. Spatial constraint, applied to all devices in a space.

7. Imiqobo yesixhobo, esetyenziswe kwisixhobo esinye.

Isoftware ilandela imiqobo eyahlukeneyo yoyilo ukusuka kwizixhobo ezizodwa ukuya kuyo yonke imithetho yoyilo, kwaye ibonisa uku-odolwa kwale mithetho kuyilo ngendlela yemizobo.

Example 1: Line width = F (impedance, layer spacing, dielectric constant, copper foil height). Nanku umzekelo wendlela imiqobo enesidima enokusetyenziswa ngayo njengemigaqo yoyilo yokulawula ukungalungelelani. Njengoko kukhankanyiwe ngasentla, i-impedance ngumsebenzi we-dielectric rhoqo, umgama ukuya kwinqanaba lomgca elikufutshane, ububanzi kunye nokuphakama kwetambo yobhedu. Ukusukela ukuba i-impedance efunekayo yoyilo igqityiwe, ezi paramitha zine zinokuthathwa ngokungenamkhethe njengezinto eziguqukayo ezifanelekileyo ukuphinda zibhale ifom ye-impedance. Kwiimeko ezininzi, abayili banokulawula ububanzi bomgca kuphela.

Because of this, the constraints on line width are functions of impedance, dielectric constant, distance to the nearest line layer, and height of the copper foil. Ukuba ifomula ichazwa njengesithintelo esinegunya lokuma kunye nenkqubo yenkqubo yokuvelisa njengesithintelo senqanaba loyilo, isoftware iya kulungelelanisa ngokuzenzekelayo ububanzi bomgca ukubuyekeza xa utshintsho lwelayini eyilelweyo. Kwangokunjalo, ukuba ibhodi yesekethe eyenziweyo iveliswa kwinkqubo eyahlukileyo kwaye ukuphakama kwefoyile yobhedu kuyatshintshwa, imigaqo efanelekileyo kwinqanaba loyilo inokuphinda ibalwe ngokuzenzekelayo ngokutshintsha iiparameter zobhedu bokuphakama.

Example 2: Device interval = Max (default interval, F (device height, detection Angle).Isibonelelo esicacileyo sokusebenzisa zombini iingxaki zeparameter kunye nokujonga umthetho woyilo kukuba indlela ebekiweyo iyaphatheka kwaye ibekwe esweni xa utshintsho loyilo lusenzeka. This example shows how device spacing can be determined by process characteristics and test requirements. The formula above shows that device spacing is a function of device height and detection Angle.

I-Angle yokufumanisa ihlala ihleli kuyo yonke ibhodi, ke inokuchazwa kwinqanaba loyilo. Xa ujonga kumatshini owahlukileyo, uyilo luphela lunokuhlaziywa ngokufaka amaxabiso amatsha kwinqanaba loyilo. Emva kokuba kufakelwe iiparameter ezintsha zomatshini, umyili unokwazi ukuba uyilo luyenzeka ngokuqhuba iDRC ukujonga ukuba ngaba isithuba sokungqubana phakathi kwexabiso sisithuba esitsha, esilula ngakumbi kunokuhlalutya, ukulungisa nokwenza izibalo ezinzima ngokungqinelana kwiimfuno zezithuba ezintsha.

Yintoni enokusetyenziselwa ukunyanzela uyilo lwePCB?

Umzekelo 3: Uyilo lwecandelo,Ukongeza ekuhleleni izinto zoyilo kunye nezithintelo, imigaqo yoyilo inokusetyenziselwa uyilo lwecandelo, Oko kukuthi, inokubona ukuba ungabeka phi izixhobo ngaphandle kokubangela iimpazamo ngokusekwe kuthintelo. Ukuqaqanjiswa kumzobo 1 kukuhlangabezana nezithintelo zomzimba (ezinje ngekhefu kunye nomphetho wesithuba seplati kunye nesixhobo) indawo yendawo yezixhobo, inani le-2 lokuqaqamba kukuhlangabezana nendawo yokubekwa kwezixhobo ezinyanzelekileyo zombane, ezinje ngobude bomgca, inani 3 libonisa kuphela indawo yesithintelo sendawo, ekugqibeleni, umzobo 4 yindawo enqamlezileyo yamalungu amathathu okuqala omfanekiso, olu luyilo lommandla osebenzayo, Devices placed in this region can satisfy all constraints.

Yintoni enokusetyenziselwa ukunyanzela uyilo lwePCB？

Ngapha koko, ukuvelisa izithintelo ngendlela yemodyuli kunokuphucula kakhulu ukugcinwa kunye nokusebenza kwakhona. New expressions can be generated by referring to the constraint parameters of different layers in the previous stage, for example, the line width of the top layer depends on the distance of the top layer and the height of the copper wire, and the variables Temp and Diel_Const in the design level. Note that design rules are displayed in descending order, and changing a higher-level constraint immediately affects all expressions that refer to that constraint.

Yintoni enokusetyenziselwa ukunyanzela uyilo lwePCB？

Uyilo lokusetyenziswa kwakhona kunye namaxwebhu

Parametric constraints, not only can significantly improve the initial design process, and reuse of engineering change and design more useful, the constraint can be used as part of the design, system and documents, if not only in engineer or designer’s mind, so when they turn to other projects may be slowly forget. Amaxwebhu esinyanzelo abhala imigaqo yokusebenza kombane ekufuneka ilandelwe ngexesha lenkqubo yoyilo kwaye inika ithuba kwabanye ukuba baqonde iinjongo zomyili ukuze le mithetho isetyenziswe ngokulula kwiinkqubo ezintsha zokuvelisa okanye itshintshwe ngokweemfuno zokusebenza kombane. Future multiplexers can also know the exact design rules and make changes by entering new process requirements without having to guess how line widths were obtained.

This article conclusion

Umhleli wesithintelo separameter uququzelela ubeko lwePCB kunye nokuhamba phantsi kwemiqobo emininzi, kwaye okokuqala yenza ukuba isoftware yokuhamba ngokuzenzekelayo kunye nemithetho yoyilo ihlolwe ngokupheleleyo ngokuchasene neemfuno zombane kunye nenkqubo, endaweni yokuxhomekeka kumava okanye kwimigaqo elula yoyilo ingasetyenziswa kangako. The result is a design that can achieve a one-time success, reducing or even eliminating prototype debugging.