Through the analysis of the parasitic characteristics of vias, we can see that in high-speed Pkb design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design:

1. Considering the cost and signal quality, choose a reasonable size via size. For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.

2. The two formulas discussed above can be concluded that using a thinner PCB is beneficial to reduce the two parasitic parameters of the via.

3. Eseye pa chanje kouch tras siyal yo sou tablo PCB la, sa vle di, eseye pa sèvi ak vias ki pa nesesè.

4. Pouvwa a ak broch tè yo ta dwe komanse fouye tou pre, ak plon ki genyen ant via a ak peny la ta dwe kout ke posib, paske yo pral ogmante enduktans la. An menm tan an, pouvwa a ak tè mennen yo ta dwe osi epè ke posib diminye enpedans.

5. Mete kèk vias ki chita toupre vias kouch siyal la pou bay bouk ki pi pre siyal la. Li se menm posib yo mete yon gwo kantite vias tè redondants sou tablo PCB la. Natirèlman, konsepsyon an bezwen fleksib. Modèl la via diskite pi bonè se ka a kote gen kousinen sou chak kouch. Pafwa, nou ka diminye oswa menm retire kousinen yo nan kèk kouch. Espesyalman lè dansite nan vias trè wo, li ka mennen nan fòmasyon nan yon Groove repo ki separe bouk la nan kouch nan kòb kwiv mete. Pou rezoud pwoblèm sa a, nan adisyon a deplase pozisyon nan via a, nou ka konsidere tou mete via a sou kouch kwiv la. Gwosè pad la redwi.