Through the analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design:

1. Considering the cost and signal quality, choose a reasonable size via size. For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.

2. The two formulas discussed above can be concluded that using a thinner PCB is beneficial to reduce the two parasitic parameters of the via.

3. Try not not to change layers of the signal traces in PCB in board, id est, try not to use not necesse vias.

4. Potestas et paxilli prope terebrari debent, et plumbum inter viam et clavum quam brevissime debet, quia inductionem augebit. Eodem tempore, potentia et terra quam crebra ad impedimentum reducere debet ducit.

5. Pone nonnullas vias fundatas prope vias signaculi strato, ut signum ansam proximam praebeas. Etiam in tabula PCB vias collocare licet numerosum numerum superuacentium locorum. Donec eget vestibulum ante. Exemplar per exemplum superius dictum est ubi pads in utroque tabulato sunt. Aliquando padum aliquorum stratorum minuere vel removere possumus. Praesertim cum densitas viarum altissima sit, efficere potest ad formationem sulcus intermissus, qui fasciam in strato aeneo separat. Ad hanc quaestionem solvendam, praeter positionem movendi viarum, etiam considerare possumus viam in strato aeneo collocare. Codex magnitudine redactus est.