Through the analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design:

1. Considering the cost and signal quality, choose a reasonable size via size. For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.

2. The two formulas discussed above can be concluded that using a thinner PCB is beneficial to reduce the two parasitic parameters of the via.

3. Ngana kia kaua e whakarereke i nga paparanga o nga tohu tohu i runga i te papa PCB, ara, me ngana kia kaua e whakamahi i nga vias kore.

4. Ko nga titi mana me te whenua me werohia ki te taha tata, me te mata i waenga i te via me te titi kia poto rawa, na te mea ka nui ake te inductance. I te wa ano, ko te mana me te arataki whenua kia rite ki te matotoru kia taea ai te whakaiti i te aukati.

5. Whakanohoia etahi vias whenua tata ki nga vias o te paparanga tohu hei whakarato i te kohanga tata mo te tohu. Ka taea hoki te whakanoho i te maha o nga vias whenua i runga i te papa PCB. Ko te tikanga, me ngawari te hoahoa. Ko te tauira ma te korero i mua ake nei ko te keehi he papa kei runga i ia paparanga. I etahi wa, ka taea e tatou te whakaiti, te tango ranei i nga papa o etahi paparanga. Ina koa ka tino tiketike te kiato o te vias, ka puta pea he riu pakaru e wehe ana i te kapiti i te paparanga parahi. Hei whakaoti i tenei raruraru, i tua atu i te neke i te tuunga o te via, ka taea ano e tatou te whakaaro ki te whakatakoto i te via ki runga i te paparanga parahi. Ka whakaitihia te rahi o te papa.