Through the analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design:

1. Considering the cost and signal quality, choose a reasonable size via size. For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.

2. The two formulas discussed above can be concluded that using a thinner PCB is beneficial to reduce the two parasitic parameters of the via.

3. Ipprova ma tibdelx is-saffi tat-traċċi tas-sinjali fuq il-bord tal-PCB, jiġifieri, ipprova ma tużax vias bla bżonn.

4. Il-brilli tal-qawwa u tal-art għandhom jittaqqbu fil-qrib, u ċ-ċomb bejn il-via u l-pin għandu jkun qasir kemm jista ‘jkun, minħabba li se jżidu l-inductance. Fl-istess ħin, iċ-ċomb tal-enerġija u tal-art għandhom ikunu ħoxnin kemm jista ‘jkun biex titnaqqas l-impedenza.

5. Poġġi xi vias ertjati ħdejn il-vias tas-saff tas-sinjal biex tipprovdi l-eqreb loop għas-sinjal. Huwa saħansitra possibbli li jitqiegħed numru kbir ta ‘vias ta’ l-art żejda fuq il-bord tal-PCB. Naturalment, id-disinn jeħtieġ li jkun flessibbli. Il-mudell tal-via diskuss qabel huwa l-każ fejn hemm pads fuq kull saff. Xi drabi, nistgħu nnaqqsu jew saħansitra nneħħu l-pads ta ‘xi saffi. Speċjalment meta d-densità tal-vias hija għolja ħafna, tista ’twassal għall-formazzjoni ta’ skanalatura tal-waqfa li tifred il-linja fis-saff tar-ram. Biex issolvi din il-problema, minbarra li ċċaqlaq il-pożizzjoni tal-via, nistgħu wkoll nikkunsidraw li npoġġu l-via fuq is-saff tar-ram. Id-daqs tal-kuxxinett jitnaqqas.