Through the analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design:

1. Considering the cost and signal quality, choose a reasonable size via size. For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.

2. The two formulas discussed above can be concluded that using a thinner PCB is beneficial to reduce the two parasitic parameters of the via.

3. Coba teu ngarobah lapisan ngambah sinyal dina dewan PCB, nyaeta, coba teu make vias perlu.

4. Kakuatan sarta taneuh pin kudu dibor caket dieu, sarta kalungguhan antara via na pin kudu jadi pondok-gancang, sabab bakal ningkatkeun induktansi. Dina waktos anu sami, kakuatan sareng taneuh kedah janten kandel sabisa pikeun ngirangan impedansi.

5. Teundeun sababaraha vias grounded deukeut vias tina lapisan sinyal nyadiakeun loop pangcaketna pikeun sinyal. Ieu malah mungkin pikeun nempatkeun angka nu gede ngarupakeun vias taneuh kaleuleuwihan dina dewan PCB. Tangtosna, desain kedah fleksibel. Modél via dibahas saméméhna nyaéta kasus dimana aya hampang dina unggal lapisan. Sakapeung, urang bisa ngurangan atawa malah nyabut hampang tina sababaraha lapisan. Utamana lamun dénsitas vias pisan tinggi, éta bisa ngakibatkeun formasi alur putus nu misahkeun loop dina lapisan tambaga. Pikeun ngajawab masalah ieu, sajaba ti pindah posisi via, urang ogé bisa mertimbangkeun nempatkeun via dina lapisan tambaga. Ukuran pad diréduksi.