Enprime Circuit Board (PCB), ke yo rele tou Printed Circuit Board (PCB), yo itilize pou konekte ak fonksyone konpozan elektwonik e se yon pati enpòtan nan konsepsyon sikwi pouvwa a. Atik sa a pral entwodui règ debaz yo nan Layout PCB ak fil elektrik.

Detaye règ debaz yo nan Layout tablo PCB ak fil elektrik

Basic rules of component layout

1. According to the layout of circuit modules, the related circuit to achieve the same function is called a module, the components in the circuit module should adopt the principle of nearby concentration, and the digital circuit and analog circuit should be separated;

2. Eleman, aparèy ak vis pa dwe enstale nan 3.5mm (pou M2.5) ak 4mm (pou M3) alantou twou yo ki pa aliye tankou twou pwezante ak twou estanda nan 1.27mm;

3. Horizontal resistance, inductor (plug-in), electrolytic capacitor and other components under the cloth hole, so as to avoid the wave soldering hole and component shell short circuit;

4. Pati ekstèn eleman an se 5mm lwen kwen plak la;

5. The distance between the outer side of the pad of mounting element and the outer side of the adjacent inserting element is greater than 2mm;

6. Metal shell components and metal parts (shielding boxes, etc.) can not touch other components, can not be close to the printed line, pad, the spacing should be greater than 2mm. The size of positioning holes, fastener mounting holes, elliptic holes and other square holes in the plate is greater than 3mm from the plate side;

7. Eleman chofaj pa ta dwe fèmen nan fil ak eleman tèmik; High-heat devices should be evenly distributed;

8. Yo ta dwe ranje priz la alantou tablo a enprime osi lwen ke posib, epi yo ta dwe ranje tèminal la nan priz la pouvwa ak bar la ki konekte nan li sou menm bò a. An patikilye, pa mete priz pouvwa ak lòt konektè soude ant konektè fasilite soude nan sa yo sipò ak konektè ak konsepsyon an ak fil elektrik nan câbles pouvwa. Yo ta dwe konsidere espas espas priz ak konektè soude pou fasilite ensèsyon ak retire ploge pouvwa;

9. Layout nan lòt konpozan:

All IC components should be aligned unilaterally, and polarity marks of polar components should be clear. Polarity marks on the same printed board should not be more than two directions. When two directions appear, the two directions should be perpendicular to each other.

10, the surface wiring should be properly dense, when the density difference is too large should be filled with mesh copper foil, the grid is greater than 8mil (or 0.2mm);

11, the patch pad can not have through holes, so as to avoid the loss of solder paste resulting in virtual welding components. Liy siyal enpòtan pa pèmèt yo pase nan pye a priz;

12, patch aliyman inilateral, direksyon karaktè ki konsistan, direksyon anbalaj ki konsistan;

13. Polar devices should be marked in the same direction as far as possible on the same board.

De, règ fil elektrik eleman yo

1. Trase zòn nan fil elektrik nan zòn nan ≤1mm soti nan kwen an tablo PCB, ak nan 1mm alantou twou a aliye, ak entèdi fil elektrik;

2. Liy kouran an lajè ke posib, pa ta dwe mwens pase 18mil; Lajè liy siyal pa ta dwe mwens pase 12mil; CPU incoming and outgoing lines should not be less than 10mil (or 8mil); Liy espas pa mwens pase 10mil;

3. Twou nòmal la pa mwens pase 30mil;

4. Double liy insert: pad 60mil, Ouverture 40mil;

1 / 4W rezistans: 51 * 55mil (0805 fèy); Dirèk insert pad 62mil, Ouverture 42mil;

Non-polar capacitor: 51*55mil (0805 sheet); Dirèk insert pad 50mil, Ouverture 28mil;

5. Remake byen ke câbles pouvwa ak câbles tè yo ta dwe radial osi lwen ke posib, ak câbles siyal pa ta dwe boukle.

Kouman amelyore kapasite anti-entèferans ak konpatibilite elektwomayetik?

Kouman amelyore kapasite anti-entèferans ak konpatibilite elektwomayetik lè w ap devlope pwodwi elektwonik ak processeur?

1. Kèk nan sistèm sa yo ta dwe peye atansyon espesyal sou entèferans anti-elektwomayetik:

(1) frekans revèy mikrokontroleur la patikilyèman wo, sik otobis la patikilyèman vit.

(2) Sistèm nan gen sikwi kondwi ki gen gwo pouvwa, ki gen gwo kouran, tankou relè etensèl, switch ki gen anpil kouran, elatriye.

(3) sistèm ak sikwi siyal analòg fèb ak segondè presizyon A / D sikwi konvèsyon.

2. Mezi sa yo pran pou ogmante kapasite entèferans anti-elektwomayetik sistèm lan:

(1) Chwazi mikrokontroleur ak frekans ki ba:

Mikrokontroleur la ak frekans revèy ki ba ekstèn ka efektivman diminye bri ak amelyore kapasite anti-entèferans nan sistèm lan. Vag kare ak vag sinis ak menm frekans lan, eleman frekans segondè vag kare a pi plis pase vag sinis. Malgre ke anplitid la nan eleman nan frekans segondè nan vag la kare se pi piti pase sa yo ki nan vag fondamantal la, ki pi wo a frekans lan, pi fasil la li se emèt yo epi yo vin yon sous bri. Ki pi enfliyan bri frekans segondè ki te pwodwi pa mikrokontroleur a se apeprè 3 fwa nan frekans revèy la.

(2) Diminye deformation nan transmisyon siyal la

Mikrokontroleur yo sitou manifaktire pa gwo vitès CMOS teknoloji. Static input current signal input at about 1 ma, around ten pf in the input capacitance, high input impedance, high speed CMOS circuit outputs are fairly on load capacity, namely the considerable output value, the output end of a door through a very long lead to the high input, the input impedance reflection problem is very serious, it will cause the signal distortion, Ogmante bri sistèm lan. Lè Tpd “Tr”, li vin yon pwoblèm liy transmisyon, yo dwe konsidere refleksyon siyal la, matche enpedans ak sou sa.

Tan an reta nan siyal la sou tablo a enprime ki gen rapò ak enpedans nan karakteristik nan plon an, se sa ki, nan konstan nan Dielectric nan materyèl la tablo enprime. Siyal yo ka apeprè konsidere vwayaje ant 1/3 ak 1/2 vitès la nan limyè sou PCB mennen. Tr a (tan reta estanda) nan eleman telefòn lojik souvan itilize nan sistèm ki fèt ak mikrokontroleur se ant 3 ak 18ns.

Sou tablo sikwi enprime a, siyal la pase nan yon rezistans 7W ak yon plon 25cm, ak yon reta sou entènèt nan apeprè 4 a 20ns. That is to say, the signal on the printed line lead as short as possible, the longest should not exceed 25cm. Ak kantite twou yo ta dwe tankou ti ke posib, de preferans pa plis pase 2.

Lè tan an monte siyal se pi vit pase tan an reta siyal, se elektwonik vit aplike. Nan pwen sa a, yo ta dwe konsidere enpedans matche liy transmisyon an. Pou transmisyon siyal ant blòk entegre sou yon tablo sikwi enprime, Td Trd ta dwe evite. Pi gwo tablo a sikwi enprime, pi vit nan sistèm lan pa ka twò vit.